Rekha K. James

According to our database, Rekha K. James authored at least 25 papers between 2006 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

ELEMENT: Energy-Efficient Multi-NoP Architecture for IMC-Based 2.5-D Accelerator for DNN Training.

K. Neethu, K. C. Sharin Shahana, Rekha K. James, John Jose, Sumit K. Mandal

IEEE Des. Test, December, 2023

Modelling and Impact Analysis of Antipode Attack in Bufferless On-Chip Networks.

Rose George Kunthara, V. R. Josna, K. Neethu, Rekha K. James, John Jose

SN Comput. Sci., May, 2023

Modelling and Impact Analysis of Push Back Attack in 3D Bufferless Network on Chip.

V. R. Josna, Rose George Kunthara, Rekha K. James, John Jose

Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

2022

Threshold Voltage Modeling of Negative Capacitance Double Gate TFET.

U. S. Shikha, Rekha K. James, Anju Pradeep, Sumi Baby, Jobymol Jacob

Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

RIBiT: Reduced Intra-flit Bit Transitions for Bufferless NoC.

Akshay Sarman, Alwin Shaju, Rose George Kunthara, K. Neethu, Rekha K. James, John Jose

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

DAReS: Deflection Aware Rerouting between Subnetworks in Bufferless On-Chip Networks.

Rose George Kunthara, Rekha K. James, Simi Zerine Sleeba, John Jose

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021

Traffic aware routing in 3D NoC using interleaved asymmetric edge routers.

Rose George Kunthara, Rekha K. James, Simi Zerine Sleeba, John Jose

Nano Commun. Networks, 2021

Dual Stage Encoding Technique to Minimize Cross Coupling across NoC Links.

S. Sharon Dev, S. M. Krishna, S. S. Archana, Rose George Kunthara, K. Neethu, Rekha K. James

Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

2019

2L-2D Routing for Buffered Mesh Network-on-Chip.

Rose George Kunthara, K. Neethu, Rekha K. James, Simi Zerine Sleeba, Tripti S. Warrier, John Jose

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

DoLaR: Double Layer Routing for Bufferless Mesh Network-on-Chip.

Rose George Kunthara, K. Neethu, Rekha K. James, Simi Zerine Sleeba, John Jose

Proceedings of the TENCON 2019, 2019

Asymmetric routing in 3D NoC using interleaved edge routers.

Rose George Kunthara, Rekha K. James, Simi Zerine Sleeba, John Jose

Proceedings of the 12th International Workshop on Network on Chip Architectures, 2019

2018

Token based Detection and Neural Network based Reconstruction framework against code injection vulnerabilities.

Teresa K. George, K. Poulose Jacob, Rekha K. James

J. Inf. Secur. Appl., 2018

Traffic Aware Deflection Rerouting Mechanism for Mesh Network on Chip.

Simi Zerine Sleeba, John Jose, Maurizio Palesi, Rekha K. James, Maniyelil Govindankutty Mini

Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

ReDC: Reduced Deflection CHIPPER Router for Bufferless NoCs.

Rose George Kunthara, Rekha K. James, Simi Zerine Sleeba, John Jose

Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018

2016

A GA Based Simple and Efficient Technique to Design Combinational Logic Circuits Using Universal Logic Modules.

C. K. Vijayakumari, Rekha K. James, P. Mythili

J. Circuits Syst. Comput., 2016

Leakage Power Minimization in Deep Sub-Micron Technology by Exploiting Positive Slacks of Dependent Paths.

Tuhin Subhra Chakraborty, Santanu Kundu, Deepak Agrawal, Sanjay Tanaji Shinde, Jacob Mathews, Rekha K. James

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2009

High Performance, Low Latency Double Digit Decimal Multiplier on ASIC and FPGA.

Rekha K. James, K. Poulose Jacob, Sreela Sasi

Proceedings of the World Congress on Nature & Biologically Inspired Computing, 2009

Double Digit Decimal Multiplier on XILINX FPGA.

Rekha K. James, K. Poulose Jacob, Sreela Sasi

Proceedings of the 2009 International Conference on Embedded Systems & Applications, 2009

2008

RNS Based Programmable Multi-Mode Decimation Filter for WCDMA and WiMAX.

Shahana Thottathikkulam Kassim, Babita R. Jose, Rekha K. James, K. Poulose Jacob, Sreela Sasi

Proceedings of the 67th IEEE Vehicular Technology Conference, 2008

Fixed Point Decimal Multiplication Using RPS Algorithm.

Rekha K. James, Shahana Thottathikkulam Kassim, K. Poulose Jacob, Sreela Sasi

Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2008

Dual-mode RNS based programmable decimation filter for WCDMA and WLANa.

Shahana Thottathikkulam Kassim, Babita R. Jose, Rekha K. James, K. Poulose Jacob, Sreela Sasi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

RRNS-Convolutional encoded concatenated code for OFDM based wireless communication.

Shahana Thottathikkulam Kassim, Babita R. Jose, Rekha K. James, K. Poulose Jacob, Sreela Sasi

Proceedings of the 16th International Conference on Networks, 2008

2007

A New Look at Reversible Logic Implementation of Decimal Adder.

Rekha K. James, Shahana Thottathikkulam Kassim, K. Poulose Jacob, Sreela Sasi

Proceedings of the International Symposium on System-on-Chip, 2007

Genetic Algorithm-Based Combinational Logic Synthesis Using Universal Logic Modules.

Shahana Thottathikkulam Kassim, Rekha K. James, K. Poulose Jacob, Sreela Sasi

Proceedings of the 2007 International Conference on Embedded Systems & Applications, 2007

2006

Delay-Reduced Combinational Logic Synthesis using Multiplexers.

Rekha K. James, Shahana Thottathikkulam Kassim, K. Poulose Jacob, Sreela Sasi

Proceedings of the 2006 International Conference on Embedded Systems & Applications, 2006