Roy P. Paily
Orcid: 0000-0003-3004-9369
According to our database1,
Roy P. Paily
authored at least 45 papers
between 2008 and 2023.
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Bibliography
2023
IEEE Internet Things J., August, 2023
2022
Int. J. Circuit Theory Appl., 2022
Design and Implementation of Adaptive Binary Divider for Fixed-Point and Floating-Point Numbers.
Circuits Syst. Signal Process., 2022
2021
A High-Performance Core Micro-Architecture Based on RISC-V ISA for Low Power Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
2020
An Efficient Architecture for QRS Detection in FPGA Using Integer Haar Wavelet Transform.
Circuits Syst. Signal Process., 2020
2019
Fabrication of Back to Back Schottky Micro-Diodes Using Silver Nanoparticle Film and Zinc Oxide Nanowire Mat for Biological Interactions.
Proceedings of the TENCON 2019, 2019
Proceedings of the TENCON 2019, 2019
Proceedings of the TENCON 2019, 2019
2017
Low-Power Digital Baseband Transceiver Design for UWB Physical Layer of IEEE 802.15.6 Standard.
IEEE Trans. Ind. Informatics, 2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
On-Chip Photovoltaic Power Harvesting System With Low-Overhead Adaptive MPPT for IoT Nodes.
IEEE Internet Things J., 2017
2016
An Efficient On-Chip Switched-Capacitor-Based Power Converter for a Microscale Energy Transducer.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
IET Comput. Digit. Tech., 2016
Multi-standard high-throughput and low-power quasi-cyclic low density parity check decoder for worldwide interoperability for microwave access and wireless fidelity standards.
IET Circuits Devices Syst., 2016
Memory-Reduced Maximum A Posteriori Probability Decoding for High-Throughput Parallel Turbo Decoders.
Circuits Syst. Signal Process., 2016
Design and Implementation of Blind Assistance System Using Real Time Stereo Vision Algorithms.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
An Efficient on Chip Power Management Architecture for Solar Energy Harvesting Systems.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Design and Implementation of Low-Power Digital Baseband Transceivers for IEEE802.15.6 Standard.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
2015
Comparative Study of Simplified MAP Algorithms and an Implementation of Non-Parallel-Radix-2 Turbo Decoder.
J. Signal Process. Syst., 2015
A New PVT Compensation Technique Based on Current Comparison for Low-Voltage, Near Sub-Threshold LNA.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
VLSI Design and Hardware Implementation of High-Speed Energy-Efficient Logarithmic-MAP Decoder.
J. Low Power Electron., 2015
An efficient on-chip energy processing circuit for micro-scale energy harvesting systems.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015
2014
High-Throughput Turbo Decoder With Parallel Architecture for LTE Wireless Communication Standards.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Fabrication and Testing of an Osmotic Pressure Sensor for Glucose Sensing Application.
Micromachines, 2014
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014
Hardware Implementation and Testing of Log-MAPP Decoder Based on Novel Un-grouped Sliding-Window Technique.
Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014
2013
Performance and throughput analysis of turbo decoder for the physical layer of digitalvideo-broadcasting-satellite-services-tohandhelds standard.
IET Commun., 2013
Design and Implementation of a High Speed MAP Decoder Architecture for Turbo Decoding.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013
A Dual Material Double-Layer Gate Stack Junctionless Transistor for Enhanced Analog Performance.
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013
A novel state metric normalization technique for high-throughput maximum-a-posteriori-probability decoder.
Proceedings of the International Conference on Advances in Computing, 2013
2012
Resonant Frequency Characteristics of a SAW Device Attached to Resonating Micropillars.
Sensors, 2012
Fpga Implementation of High Speed and Low Power Architectures for Image Segmentation using Sobel Operators.
J. Circuits Syst. Comput., 2012
Low power 2.4 GHz RF transmitter for satellite subsystem using CORDIC based frequency translator.
Proceedings of the Ninth International Conference on Wireless and Optical Communications Networks, 2012
Design and Implementation of a Linear Feedback Shift Register Interleaver for Turbo Decoding.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012
2011
Fabrication and characterisation of high-performance and high-current back-gate thin-film field-effect transistors using sorted single-walled carbon nanotubes.
IET Circuits Devices Syst., 2011
Performance Comparison of Thin-Film Transistors Fabricated Using Different Purity Semiconducting Nanotubes.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011
Proceedings of the Advances in Computing and Communications, 2011
2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
2008
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008