Tomasz Garbolino

According to our database, Tomasz Garbolino authored at least 16 papers between 1999 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

Designing of Test Pattern Generators for stimulation of crosstalk faults in bus-type connections.

Tomasz Garbolino

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2011

Optimal on-line built-in self-test structure for system-reliability improvement.

Gregor Papa, Tomasz Garbolino

Proceedings of the IEEE Congress on Evolutionary Computation, 2011

2010

Genetic algorithm for test pattern generator design - Automatic evolution of circuits.

Tomasz Garbolino, Gregor Papa

Appl. Intell., 2010

Reduced-size signature-based diagnostic dictionary for interconnection testing.

Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka

Proceedings of the 10th IFAC Workshop on Programmable Devices and Embedded Systems, 2010

How to reduce size of a signature-based diagnostic dictionary used for testing of connections.

Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009

Effective BIST for crosstalk faults in interconnects.

Tomasz Rudnicki, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka

Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

2008

Test Pattern Generator Design Optimization Based on Genetic Algorithm.

Tomasz Garbolino, Gregor Papa

Proceedings of the New Frontiers in Applied Artificial Intelligence, 2008

Deterministic Test Pattern Generator Design.

Gregor Papa, Tomasz Garbolino, Franc Novak

Proceedings of the Applications of Evolutionary Computing, 2008

Interconnect Faults Identification and Localization Using Modified Ring LFSRs.

Andrzej Hlawiczka, Krzysztof Gucwa, Tomasz Garbolino, Michal Kopec

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2007

Avoiding Crosstalk Influence on Interconnect Delay Fault Testing.

Tomasz Garbolino, Krzysztof Gucwa, Michal Kopec, Andrzej Hlawiczka

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006

Test-per-Clock Detection, Localization and Identification of Interconnect Faults.

Michal Kopec, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka

Proceedings of the 11th European Test Symposium, 2006

Detection, Localisation and Identification of Interconnection Faults Using MISR Compactor.

Tomasz Garbolino, Michal Kopec, Krzysztof Gucwa, Andrzej Hlawiczka

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2004

Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor.

Ondrej Novák, Zdenek Plíva, Jiri Nosek, Andrzej Hlawiczka, Tomasz Garbolino, Krzysztof Gucwa

J. Electron. Test., 2004

2002

Efficient test pattern generators based on specific cellular automata structures.

Tomasz Garbolino, Andrzej Hlawiczka

Microelectron. Reliab., 2002

2000

Fast and low-area TPGs based on T-type flip-flops can be easily integrated to the scan path.

Tomasz Garbolino, Andrzej Hlawiczka, Adam Kristof

Proceedings of the 5th European Test Workshop, 2000

1999

A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI Circuits.

Tomasz Garbolino, Andrzej Hlawiczka

Proceedings of the Dependable Computing, 1999