Zdenek Plíva

According to our database, Zdenek Plíva authored at least 12 papers between 2004 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

Detection of NAT64/DNS64 by SRV Records: Detection Using Global DNS Tree in the World Beyond Plain-Text DNS.

Martin Hunek, Zdenek Plíva

Proceedings of the Computer Networks - 27th International Conference, 2020

2018

Test response compaction method with improved detection and diagnostic abilities.

Ondrej Novák, Zdenek Plíva

Microelectron. Reliab., 2018

2017

Logic testing with test-per-clock pattern loading and improved diagnostic abilities.

Ondrej Novák, Zdenek Plíva

Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

Design and optimisation of NiTi pressure gauge.

Martin Hunek, Zdenek Plíva

Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

2014

A new method for in situ measurement of parameters and degradation processes in modern nanoscale programmable devices.

Petr Pfeifer, Zdenek Plíva

Microprocess. Microsystems, 2014

On reliability enhancement using adaptive core voltage scaling and variations on nanoscale FPGAs.

Petr Pfeifer, Zdenek Plíva, Pieter Weckx, Ben Kaczer

Proceedings of the 15th Latin American Test Workshop, 2014

2013

On measurement of parameters of programmable microelectronic nanostructures under accelerating extreme conditions (Xilinx 28nm XC7Z020 Zynq FPGA).

Petr Pfeifer, Zdenek Plíva

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

On performance estimation of a scalable VLIW soft-core in XILINX FPGAs.

Petr Pfeifer, Zdenek Plíva, Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus

Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012

On measurement of impact of the metallization and FPGA design to the changes of slice parameters and generation of delay faults.

Petr Pfeifer, Zdenek Plíva

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2006

Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead.

Ondrej Novák, Zdenek Plíva, Jiri Jenícek, Zbynek Mader, Michal Jarkovský

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2005

COMPAS - Compressed Test Pattern Sequencer for Scan Based Circuits.

Ondrej Novák, Jirí Zahrádka, Zdenek Plíva

Proceedings of the Dependable Computing, 2005

2004

Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor.

Ondrej Novák, Zdenek Plíva, Jiri Nosek, Andrzej Hlawiczka, Tomasz Garbolino, Krzysztof Gucwa

J. Electron. Test., 2004