Ondrej Novák

Orcid: 0000-0002-3030-0616

According to our database1, Ondrej Novák authored at least 50 papers between 1988 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Nonlinear compression block codes: Exact and random search strategy.
Microprocess. Microsystems, 2023

Deterministic Search Strategy of Compression Codes.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

2022
Nonlinear Compression Block Codes Search Strategy.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2021
Search Strategy of Large Nonlinear Block Codes.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

2020
Decompressors using nonlinear codes.
Microprocess. Microsystems, 2020

2019
International Symposium on Design and Diagnostics of Electronic Circuits and Systems.
Proceedings of the IEEE International Test Conference, 2019

Combinational Decompressors with Nonlinear Codes.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Nonlinear Compression Codes Used In IC Testing.
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

Portable Bluetooth Microsystem for Electrochemically Modulated Nitric Oxide-Releasing Catheters.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

2018
Foreword to the special issue on 20th IEEE international symposium on design and diagnostics of electronic circuits and systems (DDECS2017).
Microelectron. Reliab., 2018

Test response compaction method with improved detection and diagnostic abilities.
Microelectron. Reliab., 2018

Test Compression Using Extended Nonlinear Binary Codes.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

2017
Sequential Test Decompressors with Fast Tester Bits Wide-Spreading.
J. Circuits Syst. Comput., 2017

Extended binary nonlinear codes and their application in testing and compression.
Proceedings of the 22nd IEEE European Test Symposium, 2017

Logic testing with test-per-clock pattern loading and improved diagnostic abilities.
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

2016
An empirical model of UWB large-scale signal fading in neocortical research.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Test Decompressor Effectivity Improvement.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Sequential test decompressors with fast variable wide spreading.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015
Formation and disruption of tonotopy in a large-scale model of the auditory cortex.
J. Comput. Neurosci., 2015

Test compression for circuits with multiple scan chains.
Proceedings of the 16th Latin-American Test Symposium, 2015

LFSR Reseeding Based Test Compression Respecting Different Controllability of Decompressor Outputs.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014
A highly flexible reconfigurable system on a Xilinx FPGA.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Test-data compression with low number of channels and short test time.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2013
Relocation of reconfigurable modules on Xilinx FPGA.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

Test pattern decompression in parallel scan chain architecture.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012
An evaluation of the application dependent FPGA test method.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

On test time reduction using pattern overlapping, broadcasting and on-chip decompression.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
Scan chain configuration method for broadcast decompressor architecture.
Proceedings of the 12th Latin American Test Workshop, 2011

Advanced scan chain configuration method for broadcast decompressor architecture.
Proceedings of the 9th East-West Design & Test Symposium, 2011

Test vector overlapping based compression tool for narrow test access mechanism.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2010
Application dependent FPGA testing method using compressed deterministic test vectors.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

COMPAS - Advanced test compressor.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

Application Dependent FPGA Testing Method.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Reconfigurable Fault-Tolerant System Sychronization.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009
Structural test of programmed FPGA circuits.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

2007
A Novel Emulation Technique that Preserves Circuit Structure and Timing.
Proceedings of the International Symposium on System-on-Chip, 2007

Test Pattern Compression Based on Pattern Overlapping.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006
Conference Reports.
IEEE Des. Test Comput., 2006

Using Conflict-Based On-line Learning to Accelerate the Backtrace Algorithm Implemented in HW.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

HW Implementation of the Backtrace Algorithm with Conflict-Driven Dynamic Reconfiguration.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

FPGA-based Fault Simulator.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2005
COMPAS - Compressed Test Pattern Sequencer for Scan Based Circuits.
Proceedings of the Dependable Computing, 2005

2004
Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor.
J. Electron. Test., 2004

2003
Comparison of Test Pattern Decompression Techniques.
Proceedings of the 2003 Design, 2003

2001
Test-per-Clock Testing of the Circuits with Scan.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

Test Pattern Decompression Using a Scan Chain.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000
On Using Deterministic Test Sets in BIST.
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

1999
Pseudorandom, Weighted Random and Pseudoexhaustive Test Patterns Generated in Universal Cellular Automata.
Proceedings of the Dependable Computing, 1999

1988
Pseudoexhaustive Test Pattern Generator with Enhanced Fault Coverage.
IEEE Trans. Computers, 1988


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