Toral Shah

According to our database, Toral Shah authored at least 7 papers between 2015 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design.

Toral Shah, Anzhela Yu. Matrosova, Masahiro Fujita, Virendra Singh

J. Electron. Test., 2018

2017

Testing multiple stuck-at faults of ROBDD based combinational circuit design.

Toral Shah, Anzhela Yu. Matrosova, Binod Kumar, Masahiro Fujita, Virendra Singh

Proceedings of the 18th IEEE Latin American Test Symposium, 2017

Test pattern generation to detect multiple faults in ROBDD based combinational circuits.

Toral Shah, Anzhela Yu. Matrosova, Virendra Singh

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

2016

ROBDD based path delay fault testable combinational circuit synthesis.

Toral Shah, Virendra Singh, Anzhela Yu. Matrosova

Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

2015

PDF testability of a combinational circuit derived by covering ROBDD nodes using Invert-And-Or circuits.

Toral Shah, Anzhela Yu. Matrosova, Virendra Singh

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Simplification of fully delay testable combinational circuits.

Anzhela Yu. Matrosova, Eugeniy Mitrofanov, Toral Shah

Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Multiple stuck-at fault testability of a combinational circuit derived by covering ROBDD nodes by Invert-And-Or sub-circuits.

Anzhela Yu. Matrosova, Eugeniy Mitrofanov, Toral Shah

Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015