Toshinobu Matsuba

According to our database, Toshinobu Matsuba authored at least 4 papers between 2010 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2014

Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs.

Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada

IPSJ Trans. Syst. LSI Des. Methodol., 2014

2013

Quantitative Evaluation of Resource Sharing in High-level Synthesis Using Realistic Benchmarks.

Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada

IPSJ Trans. Syst. LSI Des. Methodol., 2013

2012

Selective Resource Sharing with RT-Level Retiming for Clock Enhancement in High-Level Synthesis.

Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada

Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

2010

Aggressive Register Unsharing Based on SSA Transformation for Clock Enhancement in High-Level Synthesis.

Toshinobu Matsuba, Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada

Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010