Travis Forbes

According to our database, Travis Forbes authored at least 8 papers between 2012 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

A 0.2-2 GHz Time-Interleaved Multistage Switched-Capacitor Delay Element Achieving 2.55-448.6 ns Programmable Delay Range and 330 ns/mm² Area Efficiency.

Travis Forbes, Benjamin Magstadt, Jesse Moody, Justine Saugen, Andrew Suchanek, Spencer Nelson

IEEE J. Solid State Circuits, 2023

2015

A low-power two-stage harmonic rejection quadrature mixer employing bias-current reuse.

Wei-Gi Ho, Travis Forbes, Ranjit Gharpurey

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

2014

A 2 GS/s Frequency-Folded ADC-Based Broadband Sampling Receiver.

Travis Forbes, Ranjit Gharpurey

IEEE J. Solid State Circuits, 2014

A 16-band channelizer employing harmonic rejection mixers with enhanced image rejection.

Vineet Kumar Singh, Travis Forbes, Wei-Gi Ho, Jaegan Ko, Ranjit Gharpurey

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

Design and Analysis of Harmonic Rejection Mixers With Programmable LO Frequency.

Travis Forbes, Wei-Gi Ho, Ranjit Gharpurey

IEEE J. Solid State Circuits, 2013

An active interference cancellation technique with harmonic rejection for a broadband channelizer.

Wei-Gi Ho, Travis Forbes, Vineet Kumar Singh, Ranjit Gharpurey

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A frequency-folded ADC architecture with digital LO synthesis.

Travis Forbes, Wei-Gi Ho, Nan Sun, Ranjit Gharpurey

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012

Embedded LO synthesis method in harmonic rejection mixers.

Travis Forbes, Ranjit Gharpurey

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012