Tristan Delizy

Orcid: 0000-0003-4642-7141

According to our database¹, Tristan Delizy authored at least 4 papers between 2017 and 2019.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

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2019

Gestion de la mémoire dynamique pour les systèmes embarqués avec mémoire hétérogène. (Heterogeneous dynamic memory management for embedded devices).

[BibT_eX]

[DOI]

Tristan Delizy

PhD thesis, 2019

Sytare: A Lightweight Kernel for NVRAM-Based Transiently-Powered Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

2018

Estimating the Impact of Architectural and Software Design Choices on Dynamic Allocation of Heterogeneous Memories.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Symposium on Rapid System Prototyping, 2018

2017

Peripheral state persistence for transiently-powered systems.

[BibT_eX]

[DOI]

Proceedings of the Global Internet of Things Summit, 2017

Tristan Delizy

Timeline

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