Tanguy Risset

Orcid: 0000-0001-9758-4900

According to our database1, Tanguy Risset authored at least 65 papers between 1990 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Audio DSP to FPGA Compilation.
Proceedings of the 34th IEEE International Conference on Application-specific Systems, 2023

2020
Intermittent Computing with Peripherals, Formally Verified.
Proceedings of the 21st ACM SIGPLAN/SIGBED International Conference on Languages, 2020

Accurate Power Consumption Evaluation for Peripherals in Ultra Low-Power embedded systems.
Proceedings of the 2020 Global Internet of Things Summit, 2020

MPU-based incremental checkpointing for transiently-powered systems.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

2019
Sytare: A Lightweight Kernel for NVRAM-Based Transiently-Powered Systems.
IEEE Trans. Computers, 2019

2018
Estimating the Impact of Architectural and Software Design Choices on Dynamic Allocation of Heterogeneous Memories.
Proceedings of the 2018 International Symposium on Rapid System Prototyping, 2018

UWB Ranging for Rapid Movements.
Proceedings of the 2018 International Conference on Indoor Positioning and Indoor Navigation, 2018

2017
Peripheral state persistence for transiently-powered systems.
Proceedings of the Global Internet of Things Summit, 2017

CalMAR - a multi-application dataflow runtime: work-in-progress.
Proceedings of the Thirteenth ACM International Conference on Embedded Software 2017 Companion, 2017

Reliable and Reproducible Radio Experiments in FIT/CorteXlab SDR Testbed: Initial Findings.
Proceedings of the Cognitive Radio Oriented Wireless Networks, 2017

2016
A New Compilation Flow for Software-Defined Radio Applications on Heterogeneous MPSoCs.
ACM Trans. Archit. Code Optim., 2016

Compressive data aggregation on mobile wireless sensor networks for sensing in bike races.
Proceedings of the 24th European Signal Processing Conference, 2016

Mixed Hardware and Software Embedded Signal Processing Methods for in-situ Analysis of Cardiac Activity.
Proceedings of the 9th International Joint Conference on Biomedical Engineering Systems and Technologies (BIOSTEC 2016), 2016

2015
Additive companding implementation to reduce ADC constraints for multiple signals digitization.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

A wireless, low-power, smart sensor of cardiac activity for clinical remote monitoring.
Proceedings of the 17th International Conference on E-health Networking, 2015

2014
Enjeux et propositions sur les architectures RF pour l'homme connecté à la société numérique.
CoRR, 2014

Full duplex prototype of OFDM on GNURadio and USRPs.
Proceedings of the 2014 IEEE Radio and Wireless Symposium, 2014

SDR for SRD: ADC specifications for reconfigurable gateways in urban sensor networks.
Proceedings of the 2014 IEEE Radio and Wireless Symposium, 2014

Distributed mobile group detection algorithms: Application to cycling race.
Proceedings of the IEEE 39th Conference on Local Computer Networks, Edmonton, AB, Canada, 8-11 September, 2014, 2014

CorteXlab: An open FPGA-based facility for testing SDR & cognitive radio networks in a reproducible environment.
Proceedings of the 2014 Proceedings IEEE INFOCOM Workshops, Toronto, ON, Canada, April 27, 2014

CorteXlab: A facility for testing cognitive radio networks in a reproducible environment.
Proceedings of the 9th International Conference on Cognitive Radio Oriented Wireless Networks and Communications, 2014

A compilation flow for parametric dataflow: Programming model, scheduling, and application to heterogeneous MPSoC.
Proceedings of the 2014 International Conference on Compilers, 2014

Live Group Detection for Mobile Wireless Sensor Networks.
Proceedings of the 9th International Conference on Body Area Networks, 2014

2012
Hardware implementation of the GPS authentication.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Software defined radio architecture survey for cognitive testbeds.
Proceedings of the 8th International Wireless Communications and Mobile Computing Conference, 2012

2011
SoC (System on Chip).
Proceedings of the Encyclopedia of Parallel Computing, 2011

Toward an energy reduction in mobile relays: Combining MIMO and multi-mode.
Proceedings of the IFIP Wireless Days Conference 2011, 2011

2010
Virtual Machine for Software Defined Radio: Evaluating the Software VM Approach.
Proceedings of the 10th IEEE International Conference on Computer and Information Technology, 2010

2009
Long-range dependence and on-chip processor traffic.
Microprocess. Microsystems, 2009

A reindexing based approach towards mapping of DAG with affine schedules onto parallel embedded systems.
J. Parallel Distributed Comput., 2009

The Radio Virtual Machine: A solution for SDR portability and platform reconfigurability.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

2008
Hardware synthesis for systems of recurrence equations with multidimensional schedule.
Int. J. Embed. Syst., 2008

2007
Master Interface for On-chip Hardware Accelerator Burst Communications.
J. VLSI Signal Process., 2007

2006
Automatic phase detection for stochastic on-chip traffic generation.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

A Generic Multi-Phase On-Chip Traffic Generation Environment.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005
Hardware/Software Interface for Multi-Dimensional Processor Arrays.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
Cycle Accurate Simulation Model Generation for SoC Prototyping.
Proceedings of the Computer Systems: Architectures, 2004

Efficient On-Chip Communications for Data-Flow IPs.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

2003
Hardware Synthesis for Multi-Dimensional Time.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

2002
Structured Scheduling of Recurrence Equations: Theory and Practice.
Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

Advances in Bit Width Selection Methodology.
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002

2001
VLSI Design Methodology for Edge-Preserving Image Reconstruction.
Real Time Imaging, 2001

Proving Properties of Multidimensional Recurrences with Application to Regular Parallel Algorithms.
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001

Uniformization of Affine Dependance Programs for Parallel Embedded System Design.
Proceedings of the 2001 International Conference on Parallel Processing, 2001

2000
Derivation of systolic algorithms for the algebraic path problem by recurrence transformations.
Parallel Comput., 2000

On the Study of VLSI Derivation for Optical Flow Estimation.
Int. J. Pattern Recognit. Artif. Intell., 2000

Interfacing compiled FPGA programs: the MMAlpha approach.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

Automatic Design of VLSI Pipelined LMS Architectures.
Proceedings of the 2000 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2000), 2000

1999
The Algebraic Path Problem Revisited.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

1998
Linear Programming Models for Scheduling Systems of Affine Recurrence Equations - A Comparative Study.
Proceedings of the Tenth Annual ACM Symposium on Parallel Algorithms and Architectures, 1998

1997
On Manipulating <i>Z</i>-Polyhedra Using a Canonical Representation.
Parallel Process. Lett., 1997

Hierarchical Static Analysis for Improving the Complexity of Linear Algebra Algorithms.
Proceedings of the Parallel Computing: Fundamentals, 1997

1996
Resource-constrained scheduling of partitioned algorithms on processor arrays.
Integr., 1996

Extension Of The Alpha Language To Recurrences On Sparse Periodic Domains.
Proceedings of the 1996 International Conference on Application-Specific Systems, 1996

1995
Construction of Do Loops from Systems of Affine Constraints.
Parallel Process. Lett., 1995

Precise Tiling for Uniform Loop Nests.
Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

1994
(Pen)-ultimate tiling?
Integr., 1994

Applying Semi-Systolic Techniques to SIMD Programming.
Proceedings of the Applications in Parallel and Distributed Computing, 1994

1993
A real-time systolic algorithm for on-the-fly hidden surface removal.
Proceedings of the International Conference on Application-Specific Array Processors, 1993

1992
A method to synthesize modular systolic arrays with local broadcast facility.
Proceedings of the Application Specific Array Processors, 1992

1991
Synthesis of Processor Arrays for the Algebraic Path Problem: Unifying Old Results and Deriving New Architectures.
Parallel Process. Lett., 1991

Linear systolic arrays for matrix multiplication: comparisons of existing synthesis methods and new results.
Proceedings of the Algorithms and Parallel VLSI Architectures II, 1991

Uniform but non-local DAGS: a trade-off between pure systolic and SIMD solutions.
Proceedings of the Application Specific Array Processors, 1991

Synthesizing systolic arrays: some recent developments.
Proceedings of the Application Specific Array Processors, 1991

1990
Implementing Gaussian elimination on a matrix-matrix multiplication systolic array.
Parallel Comput., 1990


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