Tryggve Fossum

According to our database, Tryggve Fossum authored at least 9 papers between 1985 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

Simulating stencil-based application on future Xeon Phi processor.

Chitra Natarajan, Carl J. Beckmann, Anthony Nguyen, Mauricio Araya-Polo, Tryggve Fossum, Detlef Hohl

Proceedings of the 6th International Workshop on Performance Modeling, 2015

2013

Using in-flight chains to build a scalable cache coherence protocol.

Samantika Subramaniam, Simon C. Steely Jr., William Hasenplaugh, Aamer Jaleel, Carl J. Beckmann, Tryggve Fossum, Joel S. Emer

ACM Trans. Archit. Code Optim., 2013

2011

DEC Alpha.

Joel S. Emer, Tryggve Fossum

Proceedings of the Encyclopedia of Parallel Computing, 2011

2008

Multi Core Design for Chip Level Multiprocessing.

Tryggve Fossum

Proceedings of the Advanced Lectures on Software Engineering, 2008

2007

On-Die Interconnect and Other Challenges for Chip-Level Multi-Processing.

Tryggve Fossum

Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects, 2007

2004

Cache Scrubbing in Microprocessors: Myth or Necessity?

Shubhendu S. Mukherjee, Joel S. Emer, Tryggve Fossum, Steven K. Reinhardt

Proceedings of the 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2004), 2004

1990

Designing a VAX for high performance.

Tryggve Fossum, David B. Fite

Proceedings of the Intellectual Leverage: Thirty-Fifth IEEE Computer Society International Conference, 1990

1985

The Microarchitecture of the VAX 8600.

Fernando C. Colón Osorio, Tryggve Fossum, William Hilliard, William Brucket, Paul Guglielmo, John Bloem

Proceedings of the Spring COMPCON'85, 1985

Floating Point Processor for the VAX 8600.

Tryggve Fossum, William J. Grundmann, Virginia Blaha

Proceedings of the Spring COMPCON'85, 1985