Tushar Dhabal Das

According to our database, Tushar Dhabal Das authored at least 2 papers between 2016 and 2018.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2018

A Novel Gating Approach to Alleviate Power and Ground Noise in Silicon Chips.

Alak Majumder, Pritam Bhattacharjee, Tushar Dhabal Das

J. Circuits Syst. Comput., 2018

2016

A 90 nm leakage control transistor based clock gating for low power flip flop applications.

Pritam Bhattacharjee, Alak Majumder, Tushar Dhabal Das

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016