Tzu-Heng Huang

According to our database1, Tzu-Heng Huang authored at least 14 papers between 2016 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
Shrinking the Generation-Verification Gap with Weak Verifiers.
CoRR, June, 2025

Time To Impeach LLM-as-a-Judge: Programs are the Future of Evaluation.
CoRR, June, 2025

R&B: Domain Regrouping and Data Mixture Balancing for Efficient Foundation Model Training.
CoRR, May, 2025

ScriptoriumWS: A Code Generation Assistant for Weak Supervision.
CoRR, February, 2025

Evaluating Sample Utility for Data Selection by Mimicking Model Weights.
CoRR, January, 2025

2024
MoRe Fine-Tuning with 10x Fewer Parameters.
CoRR, 2024

Multimodal Data Curation via Object Detection and Filter Ensembles.
CoRR, 2024

The ALCHEmist: Automated Labeling 500x CHEaper than LLM Data Annotators.
Proceedings of the Advances in Neural Information Processing Systems 38: Annual Conference on Neural Information Processing Systems 2024, 2024

2023
Geometry-Aware Adaptation for Pretrained Models.
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023

Train 'n Trade: Foundations of Parameter Markets.
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023

2022
AutoWS-Bench-101: Benchmarking Automated Weak Supervision with 100 Labels.
Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022

2021
Modular Neural Networks with Fully Convolutional Networks for Typhoon-Induced Short-Term Rainfall Predictions.
Sensors, 2021

2020
Key sensor discovery for quality audit of air sensor networks.
Proceedings of the MobiSys '20: The 18th Annual International Conference on Mobile Systems, 2020

2016
A wide-range clock signal generation scheme for speed grading of a logic core.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016


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