Shi-Yu Huang

IEEE Trans. Very Large Scale Integr. Syst., March, 2023

Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization.

[BibT_eX]

[DOI]

Yung-Chuan Su

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Compiler of Reed-Solomon Codec for 400-Gb/s IEEE 802.3bs Standard.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Cell-Based Aging Sensor Using Built-In Speed Grading.

[BibT_eX]

[DOI]

Ont-Derh Lin

Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023

Optimization of DCO Using Latch-Based Varactor Cells for a Cell-Based PLL.

[BibT_eX]

[DOI]

Yi-Sheng Wang

Hsiang-Kai Teng

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Trustworthy Lifetime Prediction by Aging History Analysis and Multi-Level Stress Test.

[BibT_eX]

[DOI]

Chen-Lin Tsai

Proceedings of the IEEE International Test Conference in Asia, 2023

Self-Sufficient Clock Jitter Measurement Methodology Using Dithering-Based Calibration.

[BibT_eX]

[DOI]

Yi-Hsuan Lee

Proceedings of the IEEE International Test Conference in Asia, 2023

Low Latency Edge Classification GNN for Particle Trajectory Tracking on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

2022

Tiny Phase-Error Monitor for Fault and Soft-Error-Tolerant DLL to Support Graceful Degradation and Module-Level Testing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Process-Resilient Fault-Tolerant Delay-Locked Loop Using TMR With Dynamic Timing Correction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Graph Neural Networks for Charged Particle Tracking on FPGAs.

[BibT_eX]

[DOI]

Frontiers Big Data, 2022

On-Chip Jitter Learning for PLL.

[BibT_eX]

[DOI]

IEEE Des. Test, 2022

Just-Enough Stress Test for Infant-Mortality Screening Using Speed Binning.

[BibT_eX]

[DOI]

Chen-Lin Tsai

Proceedings of the IEEE International Test Conference, 2022

Just-Enough Strategy for Accurate Clock Jitter Measurement Using A Cyclic Time-to-Digital Converter.

[BibT_eX]

[DOI]

Yung-Chuan Su

Proceedings of the 19th International SoC Design Conference, 2022

2021

Online Safety Checking for Delay Locked Loops via Embedded Phase Error Monitor.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2021

Graph Neural Networks for Charged Particle Tracking on FPGAs.

[BibT_eX]

[DOI]

CoRR, 2021

A Duty-Cycle Monitor Supporting A Wide Frequency Range of Clock Signal.

[BibT_eX]

[DOI]

Chen-Lin Tsai

Proceedings of the IEEE International Test Conference in Asia, 2021

Rigorous Test Flow for PLL to Identify Weak Devices.

[BibT_eX]

[DOI]

Yi-Hsuan Lee

Proceedings of the IEEE International Test Conference in Asia, 2021

2020

Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Time-to-Digital Converter Compiler for On-Chip Instrumentation.

[BibT_eX]

[DOI]

IEEE Des. Test, 2020

Rapid PLL Monitoring By A Novel min-MAX Time-to-Digital Converter.

[BibT_eX]

[DOI]

Chu-Chun Hsu

Proceedings of the IEEE International Test Conference, 2020

A Voting Phase Detector Design with Mitigated Process Variation.

[BibT_eX]

[DOI]

Derek Lin

Proceedings of the International SoC Design Conference, 2020

Duty-Cycle Correction For A Super-Wide Frequency Range from 10MHz to 1.2GHz.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Fault and Soft Error Tolerant Delay-Locked Loop.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Asian Test Symposium, 2020

Overview of On-Chip Performance Monitors for Clock Signals.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019

A Ping-Pong Methodology for Boosting the Resilience of Cell-Based Delay-Locked Loop.

[BibT_eX]

[DOI]

Zheng-Hong Zhang

IEEE Access, 2019

Cloud-Based Online Ageing Monitoring for IoT Devices.

[BibT_eX]

[DOI]

Guan-Hao Lian

Wei-yi Chen

IEEE Access, 2019

A Cell-Based Wide-Frequency-Range DLL Supporting Fast Frequency Scaling.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

International Test Conference in Asia (ITC-Asia) - Bridging ITC and Test Community in Asia.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2019

Overall Strategy for Online Clock System Checking Supporting Heterogeneous Integration.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2019

Online Testing of Clock Delay Faults in a Clock Network.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2019

The Ping-Pong Tunable Delay Line In A Super-Resilient Delay-Locked Loop.

[BibT_eX]

[DOI]

Zheng-Hong Zhang

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Improving scan chain diagnostic accuracy using multi-stage artificial neural networks.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

Circuit and Methodology for Testing Small Delay Faults in the Clock Network.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

A Cell-Based Fractional-N Phase-Locked Loop Compiler.

[BibT_eX]

[DOI]

Cheng-En Lee

Proceedings of the 15th International Conference on Synthesis, 2018

A Folded Locking Scheme for the Long-Range Delay Block in a Wide-Range DLL.

[BibT_eX]

[DOI]

Yu-Chi Wei

Proceedings of the International SoC Design Conference, 2018

2017

Test strategies for the clock and power distribution networks in a multi-die IC.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

Resilient Cell-Based Architecture for Time-to-Digital Converter.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

DLL-Assisted Clock Synchronization Method for Multi-Die ICs.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Cloud-Based PVT Monitoring System for IoT Devices.

[BibT_eX]

[DOI]

Guan-Hao Lian

Wei-yi Chen

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

Delay Characterization and Testing of Arbitrary Multiple-Pin Interconnects.

[BibT_eX]

[DOI]

IEEE Des. Test, 2016

Versatile Transition-Time Monitoring for Interconnects via Distributed TDC.

[BibT_eX]

[DOI]

IEEE Des. Test, 2016

Online slack-time binning for IO-registered die-to-die interconnects.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Test Conference, 2016

Cell-based delay locked loop compiler.

[BibT_eX]

[DOI]

Pei-Ching Huang

Proceedings of the International SoC Design Conference, 2016

A wide-range clock signal generation scheme for speed grading of a logic core.

[BibT_eX]

[DOI]

Proceedings of the International Conference on High Performance Computing & Simulation, 2016

Testing of small delay faults in a clock network.

[BibT_eX]

[DOI]

Proceedings of the 21th IEEE European Test Symposium, 2016

Die-to-Die Clock Skew Characterization and Tuning for 2.5D ICs.

[BibT_eX]

[DOI]

Chih-Chieh Zheng

Proceedings of the 25th IEEE Asian Test Symposium, 2016

Pre-Bond and Post-Bond Testing of TSVs and Die-to-Die Interconnects.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015

The Design and Experiments of A SID-Based Power-Aware Simulator for Embedded Multicore Systems.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2015

General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Nonintrusive On-Line Transition-Time Binning and Timing Failure Threat Detection for Die-to-Die Interconnects.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Monitoring the delay of long interconnects via distributed TDC.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Test Conference, 2015

Feedback-bus oscillation ring: a general architecture for delay characterization and test of interconnects.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Cell-based programmable phase shifter design for pulsed radar SoC.

[BibT_eX]

[DOI]

Jinn-Yann Liu

Ta-Shun Chu

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Temperature-aware online testing of power-delivery TSVs.

[BibT_eX]

[DOI]

Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014

Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration.

[BibT_eX]

[DOI]

Pei-Ying Chao

IEEE Trans. Very Large Scale Integr. Syst., 2014

Pulse-Vanishing Test for Interposers Wires in 2.5-D IC.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

PLL-Assisted Timing Circuit for Accurate TSV Leakage Binning.

[BibT_eX]

[DOI]

Li-Ren Huang

IEEE Des. Test, 2014

On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE European Test Symposium, 2014

On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

AC-Plus Scan Methodology for Small Delay Testing and Characterization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Cell-Based Process Resilient Multiphase Clock Generation.

[BibT_eX]

[DOI]

Ruo-Ting Ding

IEEE Trans. Very Large Scale Integr. Syst., 2013

Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Die-to-Die Clock Synchronization for 3-D IC Using Dual Locking Mechanism.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Programmable Leakage Test and Binning for TSVs With Self-Timed Timing Control.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Oscillation-Based Prebond TSV Test.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Worst-case IR-drop monitoring with 1GHz sampling rate.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Delay testing and characterization of post-bond interposer wires in 2.5-D ICs.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Test Conference, 2013

At-speed BIST for interposer wires supporting on-the-spot diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Mid-bond Interposer Wire Test.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

2012

High-Performance SIFT Hardware Accelerator for Real-Time Image Feature Extraction.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2012

A UWB IR timed-array radar using time-shifted direct-sampling architecture.

[BibT_eX]

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2012

Cyclic-MPCG: Process-resilient and super-resolution multi-phase clock generation by exploiting the cyclic property.

[BibT_eX]

[DOI]

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

A unified method for parametric fault characterization of post-bond TSVs.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Test Conference, 2012

Small delay testing for TSVs in 3-D ICs.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Programmable Leakage Test and Binning for TSVs.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011

A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme.

[BibT_eX]

[DOI]

Hsuan-Jung Hsu

IEEE Trans. Very Large Scale Integr. Syst., 2011

P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation.

[BibT_eX]

[DOI]

Cheng-Hung Lo

IEEE J. Solid State Circuits, 2011

A Light-and-Fast SLAM Algorithm for Robots in Indoor Environments Using Line Segment Map.

[BibT_eX]

[DOI]

J. Robotics, 2011

Speeding Up Emulation-Based Diagnosis Techniques for Logic Cores.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2011

A fully cell-based design for timing measurement of memory.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2011

Black-box leakage power modeling for cell library and SRAM compiler.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designs.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

2010

Split-Masking: An Output Masking Scheme for Effective Compound Defect Diagnosis in Scan Architecture With Test Compression.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Power aware SID-based simulator for embedded multicore DSP subsystems.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

Performance Characterization of TSV in 3D IC via Sensitivity Analysis.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

PAC duo system power estimation at ESL.

[BibT_eX]

[DOI]

Wen-Tsan Hsieh

Jen-Chieh Yeh

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

QC-Fill: Quick-and-Cool X-Filling for Multicasting-Based Scan Test.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Layout-Based Defect-Driven Diagnosis for Intracell Bridging Defects.

[BibT_eX]

[DOI]

Han-Chia Cheng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Resilient Self-V<sub>DD</sub>-Tuning Scheme With Speed-Margining for Low-Power SRAM.

[BibT_eX]

[DOI]

Hsuan-Jung Hsu

IEEE J. Solid State Circuits, 2009

Robust SRAM Design via BIST-Assisted Timing-Tracking (BATT).

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2009

QC-Fill: An X-Fill method for quick-and-cool scan test.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

2008

A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques.

[BibT_eX]

[DOI]

Jheng-Syun Yang

ACM Trans. Design Autom. Electr. Syst., 2008

A low-power SRAM for Viterbi decoder in wireless communication.

[BibT_eX]

[DOI]

Shin-Pao Cheng

IEEE Trans. Consumer Electron., 2008

A Resilient and Power-Efficient Automatic-Power-Down Sense Amplifier for SRAM Design.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

X-Calibration: A Technique for Combating Excessive Bitline Leakage Current in Nanometer SRAM Designs.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2008

UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2008

Two-Gear Low-Power Scan Test.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Diagnosis by Image Recovery: Finding Mixed Multiple Timing Faults in a Scan Chain.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2007

Robust paradigm for diagnosing hold-time faults in scan chains.

[BibT_eX]

[DOI]

J.-J. Hsu

IET Comput. Digit. Tech., 2007

RT-level vector selection for realistic peak power simulation.

[BibT_eX]

[DOI]

Chia-Chien Weng

Ching-Shang Yang

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Built-In Speed Grading with a Process-Tolerant ADPLL.

[BibT_eX]

[DOI]

Hsuan-Jung Hsu

Chun-Chieh Tu

Proceedings of the 16th Asian Test Symposium, 2007

2006

Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults.

[BibT_eX]

[DOI]

Yu-Chiun Lin

J. Electron. Test., 2006

A network security processor design based on an integrated SOC design and test platform.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

2005

Low-cost logarithmic CMOS image sensing by nonlinear analog-to-digital conversion.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2005

A low-power SRAM design using quiet-bitline architecture.

[BibT_eX]

[DOI]

Shin-Pao Cheng

Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

Quick Scan Chain Diagnosis Using Signal Profiling.

[BibT_eX]

[DOI]

Jheng-Syun Yang

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Power estimation starategies for a low-power security processor.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

A Fading Algorithm For Sequential Fault Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

2003

Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults.

[BibT_eX]

[DOI]

J. Inf. Sci. Eng., 2003

A Symbolic Inject-and-Evaluate Paradigm for Byzantine Fault Diagnosis.

[BibT_eX]

[DOI]

J. Electron. Test., 2003

Combinational circuit fault diagnosis using logic emulation.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Decomposition of Extended Finite State Machine for Low Power Design.

[BibT_eX]

[DOI]

MingHung Lee

TingTing Hwang

Proceedings of the 2003 Design, 2003

Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple Faults.

[BibT_eX]

[DOI]

Yu-Chiun Lin

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Improving the Timing of Extended Finite State Machines Via Catalyst.

[BibT_eX]

[DOI]

VLSI Design, 2002

Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm.

[BibT_eX]

[DOI]

Horng-Bin Wang

Jing-Reng Huang

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Diagnosis Of Byzantine Open-Segment Faults.

[BibT_eX]

[DOI]

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

Verifying sequential equivalence using ATPG techniques.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2001

On Improving the Accuracy Of Multiple Defect Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters.

[BibT_eX]

[DOI]

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

On speeding up extended finite state machines using catalyst circuitry.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2001, 2001

Towards the logic defect diagnosis for partial-scan designs.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2001, 2001

2000

AQUILA: An Equivalence Checking System for Large Sequential Designs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2000

High Performance/Delay Testing.

[BibT_eX]

[DOI]

Sudhakar M. Reddy

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

AutoFix: a hybrid tool for automatic logic rectification.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

ErrorTracer: design error diagnosis based on fault simulation techniques.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Fault emulation: A new methodology for fault grading.

[BibT_eX]

[DOI]

Wei-Jin Dai

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

1998

Fault-Simulation Based Design Error Diagnosis for Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the 35th Conference on Design Automation, 1998

A Hybrid Power Model for RTL Power Estimation.

[BibT_eX]

[DOI]

Proceedings of the ASP-DAC '98, 1998

1997

Incremental logic rectification.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

AQUILA: An equivalence verifier for large sequential circuits.

[BibT_eX]

[DOI]

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

An ATPG-Based Framework for Verifying Sequential Equivalence.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

A novel methodology for transistor-level power estimation.

[BibT_eX]

[DOI]

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

On Verifying the Correctness of Retimed Circuits.

[BibT_eX]

[DOI]

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

Compact Vector Generation for Accurate Power Simulation.

[BibT_eX]

[DOI]

Proceedings of the 33st Conference on Design Automation, 1996

Error Correction Based on Verification Techniques.

[BibT_eX]

[DOI]

Proceedings of the 33st Conference on Design Automation, 1996

1995

Fault emulation: a new approach to fault grading.

[BibT_eX]

[DOI]