Kun-Han Tsai

Huawei Li

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Test Challenges of Intel IA Cores.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2020

GPU-based Hybrid Parallel Logic Simulation for Scan Patterns.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2020

2019

Race and Glitch Handling: A Test Perspective.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2019

TEA: A Test Generation Algorithm for Designs with Timing Exceptions.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE Asian Test Symposium, 2019

Improving scan chain diagnostic accuracy using multi-stage artificial neural networks.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

Circuit and Methodology for Testing Small Delay Faults in the Clock Network.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

X-Sources Analysis for Improving the Test Quality.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2018

2017

Test Coverage Analysis for Designs with Timing Exceptions.

[BibT_eX]

[DOI]

Srinivasan Gopalakrishnan

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

Delay Characterization and Testing of Arbitrary Multiple-Pin Interconnects.

[BibT_eX]

[DOI]

IEEE Des. Test, 2016

Versatile Transition-Time Monitoring for Interconnects via Distributed TDC.

[BibT_eX]

[DOI]

IEEE Des. Test, 2016

Online slack-time binning for IO-registered die-to-die interconnects.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Test Conference, 2016

A wide-range clock signal generation scheme for speed grading of a logic core.

[BibT_eX]

[DOI]

Proceedings of the International Conference on High Performance Computing & Simulation, 2016

Testing of small delay faults in a clock network.

[BibT_eX]

[DOI]

Proceedings of the 21th IEEE European Test Symposium, 2016

2015

General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Nonintrusive On-Line Transition-Time Binning and Timing Failure Threat Detection for Die-to-Die Interconnects.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Clock-domain-aware test for improving pattern compression.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design, Automation and Test, 2015

A test-application-count based learning technique for test time reduction.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design, Automation and Test, 2015

Monitoring the delay of long interconnects via distributed TDC.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Test Conference, 2015

Feedback-bus oscillation ring: a general architecture for delay characterization and test of interconnects.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Pulse-Vanishing Test for Interposers Wires in 2.5-D IC.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE European Test Symposium, 2014

Testability-Driven Fault Sampling for Deterministic Test Coverage Estimation of Large Designs.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Programmable Leakage Test and Binning for TSVs With Self-Timed Timing Control.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Oscillation-Based Prebond TSV Test.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Improve speed path identification with suspect path expressions.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Design rule check on the clock gating logic for testability and beyond.

[BibT_eX]

[DOI]

Shuo Sheng

Proceedings of the 2013 IEEE International Test Conference, 2013

Delay testing and characterization of post-bond interposer wires in 2.5-D ICs.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Test Conference, 2013

At-speed BIST for interposer wires supporting on-the-spot diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Multicycle-aware At-speed Test Methodology.

[BibT_eX]

[DOI]

Xijiang Lin

Proceedings of the 22nd Asian Test Symposium, 2013

Mid-bond Interposer Wire Test.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

2012

A unified method for parametric fault characterization of post-bond TSVs.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Test Conference, 2012

Small delay testing for TSVs in 3-D ICs.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Programmable Leakage Test and Binning for TSVs.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2010

Test cycle power optimization for scan-based designs.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

A scalable quantitative measure of IR-drop effects for scan pattern generation.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

A Low Complexity Transmitter Architecture and Its Application to PAPR Reduction in SFBC MIMO-OFDM Systems.

[BibT_eX]

[DOI]

Chih-Peng Li

Sen-Hung Wang

Proceedings of IEEE International Conference on Communications, 2010

Scan based speed-path debug for a microprocessor.

[BibT_eX]

[DOI]

Proceedings of the 15th European Test Symposium, 2010

Improved weight assignment for logic switching activity during at-speed test pattern generation.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Timing-Aware Multiple-Delay-Fault Diagnosis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Speed-Path Debug Using At-Speed Scan Test Patterns.

[BibT_eX]

[DOI]

Ruifeng Guo

Wu-Tung Cheng

Proceedings of the 14th IEEE European Test Symposium, 2009

At-Speed Scan Test Method for the Timing Optimization and Calibration.

[BibT_eX]

[DOI]

Ruifeng Guo

Wu-Tung Cheng

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

Improving the Resolution of Single-Delay-Fault Diagnosis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A Robust Automated Scan Pattern Mismatch Debugger.

[BibT_eX]

[DOI]

Ruifeng Guo

Wu-Tung Cheng

Proceedings of the 17th IEEE Asian Test Symposium, 2008

Enhancing Transition Fault Model for Delay Defect Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Enhanced testing of clock faults.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Test Conference, 2007

Test Generation in the Presence of Timing Exceptions and Constraints.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

2006

Analysis and methodology for multiple-fault diagnosis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Improved Handling of False and Multicycle Paths in ATPG.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Test Conference, 2006

Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Test Conference, 2006

Delay Fault Diagnosis for Non-Robust Test.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects.

[BibT_eX]

[DOI]

Proceedings of the 15th Asian Test Symposium, 2006

At-Speed Testing with Timing Exceptions and Constraints-Case Studies.

[BibT_eX]

[DOI]

Proceedings of the 15th Asian Test Symposium, 2006

2005

Delay-fault diagnosis using timing information.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Compression mode diagnosis enables high volume monitoring diagnosis flow.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Built-in constraint resolution.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004

Realizing High Test Quality Goals with Smart Test Resource Usage.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Diagnosis of Hold Time Defects.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Compactor Independent Direct Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

An Efficient and Effective Methodology on the Multiple Fault Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Impact of Multiple-Detect Test Patterns on Product Quality.

[BibT_eX]

[DOI]

Brady Benware

Chris Schuermyer

Sreenevasan Ranganathan

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Multiple Fault Diagnosis Using n-Detection Tests.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

2002

Embedded Deterministic Test for Low-Cost Manufacturing Test.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2000

Star test: the theory and its applications.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

1997

Scan-Encoded Test Pattern Generation for BIST.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

STARBIST: Scan Autocorrelated Random Pattern Generation.

[BibT_eX]

[DOI]

Sybille Hellebrand