Uday Dasgupta

According to our database1, Uday Dasgupta authored at least 9 papers between 1999 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

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Bibliography

2016
Low voltage 2-stage and 3-stage push-pull output amplifiers in 65-nm CMOS technology.
Proceedings of the International Symposium on Integrated Circuits, 2016

2015
A Sub-1-V 65-nm MOS Threshold Monitoring-Based Voltage Reference.
IEEE Trans. Very Large Scale Integr. Syst., 2015

2014
A LDO Regulator With Weighted Current Feedback Technique for 0.47 nF-10 nF Capacitive Load.
IEEE J. Solid State Circuits, 2014

9.1 A self-calibrating NFC SoC with a triple-mode reconfigurable PLL and a single-path PICC-PCD receiver in 0.11μm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A versatile three-stage operational amplifier with Second-stage Bypass Compensation.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

An asynchronous sub-two-step quantizer for continuous-time sigma-delta modulators.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2009
High Power-supply Rejection Low Drop-out Regulator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2003
Effects of resistive loading on unity gain frequency of two-stage CMOS operational amplifiers.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

1999
Low-voltage linear OTA with rail-to-rail differential mode input signal capability.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999


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