Udi Virobnik
  According to our database1,
  Udi Virobnik
  authored at least 9 papers
  between 2009 and 2025.
  
  
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
  2025
A 7-bit 1.75-GS/s 6.9-fJ/conv.-step FoMw Loop-Unrolled Fully Asynchronous SAR ADC in 3-nm CMOS for a 224-Gb/s SerDes Receiver.
    
  
    IEEE J. Solid State Circuits, April, 2025
    
  
    IEEE J. Solid State Circuits, January, 2025
    
  
  2024
    Proceedings of the IEEE International Solid-State Circuits Conference, 2024
    
  
  2023
A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels.
    
  
    IEEE J. Solid State Circuits, 2023
    
  
  2022
    Proceedings of the IEEE International Solid-State Circuits Conference, 2022
    
  
  2020
    IEEE J. Solid State Circuits, 2020
    
  
  2019
    Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
    
  
A 1.64mW Differential Super Source-Follower Buffer with 9.7GHz BW and 43dB PSRR for Time-Interleaved ADC Applications in 10nm.
    
  
    Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
    
  
  2009
Standard CMOS Fabrication of a Sensitive Fully Depleted Electrolyte-Insulator-Semiconductor Field Effect Transistor for Biosensor Applications.
    
  
    Sensors, 2009