Ajay Balankutty

According to our database1, Ajay Balankutty authored at least 20 papers between 2007 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels.
IEEE J. Solid State Circuits, 2023

2022
A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET.
IEEE J. Solid State Circuits, 2022

A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss Compensation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021
A 56GHz Receiver Analog Front End for 224Gb/s PAM-4 SerDes in 10nm CMOS.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

8.1 A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
8.1 Lakefield and Mobility Compute: A 3D Stacked 10nm and 22FFL Hybrid Processor System in 12×12mm<sup>2</sup>, 1mm Package-on-Package.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A 112 Gb/s PAM-4 56 Gb/s NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET.
IEEE J. Solid State Circuits, 2019

56G/112G Link Foundations Standards, Link Budgets & Models.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2015
3.5 A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014

2013
A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver.
IEEE J. Solid State Circuits, 2013

2012
A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012


2011
An Ultra-Low Voltage, Low-Noise, High Linearity 900-MHz Receiver With Digitally Calibrated In-Band Feed-Forward Interferer Cancellation in 65-nm CMOS.
IEEE J. Solid State Circuits, 2011

A 12-element 60GHz CMOS phased array transmitter on LTCC package with integrated antennas.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
A 0.6-V Zero-IF/Low-IF Receiver With Integrated Fractional-N Synthesizer for 2.4-GHz ISM-Band Applications.
IEEE J. Solid State Circuits, 2010

2008
A 2.4-GHz ISM-Band Sliding-IF Receiver With a 0.5-V Supply.
IEEE J. Solid State Circuits, 2008

A 0.6V 32.5mW Highly Integrated Receiver for 2.4GHz ISM-Band Applications.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
Mismatch Characterization of Ring Oscillators.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007


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