Umer I. Cheema

Orcid: 0000-0001-9960-1305

According to our database1, Umer I. Cheema authored at least 9 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2024
Efficient Hardware Acceleration of Emerging Neural Networks for Embedded Machine Learning: An Industry Perspective.
Proceedings of the Embedded Machine Learning for Cyber-Physical, 2024

2017
Memory-Optimized Re-Gridding Architecture for Non-Uniform Fast Fourier Transform.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Power-efficient and highly scalable parallel graph sampling using FPGAs.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

FPGA-based Hardware Accelerator for Image Reconstruction in Magnetic Resonance Imaging (Abstract Only).
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

2015
InvArch: A hardware eficient architecture for Matrix Inversion.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

MedianPipes: An FPGA based Highly Pipelined and Scalable Technique for Median Filtering (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

2014
Power-efficient re-gridding architecture for accelerating Non-uniform Fast Fourier Transform.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Memory Optimized Re-gridding for Non-uniform Fast Fourier Transform on FPGAs.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

2013
A high performance architecture for computing burrows-wheeler transform on FPGAs.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013


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