Deepak Mathaikutty

Avinash Lakshminarayana

Alberto L. Sangiovanni-Vincentelli

J. Low Power Electron., 2009

Metamodeling: An Emerging Representation Paradigm for System-Level Design.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2009

Accurate power estimation of hardware co-processors using system level simulation.

[BibT_eX]

[DOI]

Sumit Ahuja

Avinash Lakshminarayana

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Power estimation methodology for a high-level synthesis framework.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Metamodeling-Driven IP Reuse for SoC Integration and Microprocessor Design.

[BibT_eX]

[DOI]

Sandeep Kumar Shukla

Artech House, ISBN: 978-1-59693-424-5, 2009

2008

A Trace-Based Framework for Verifiable GALS Composition of IPs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

MCF: A Metamodeling-Based Component Composition Framework - Composing SystemC IPs for Executable System Models.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

MMV: A Metamodeling Based Microprocessor Validation Environment.

[BibT_eX]

[DOI]

David J. Lilja

IEEE Trans. Very Large Scale Integr. Syst., 2008

Mining metadata for composability of IPs from SystemC IP library.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2008

SML-Sys: a functional framework with multiple models of computation for modeling heterogeneous system.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2008

Applying Verification Collaterals for Accurate Power Estimation.

[BibT_eX]

[DOI]

Sumit Ahuja

Proceedings of the Ninth International Workshop on Microprocessor Test and Verification, 2008

Formal Transformation of a KPN Specification to a GALS Implementation.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2008

2007

Metamodeling Driven IP Reuse for System-on-chip Integration and Microprocessor Design.

[BibT_eX]

[DOI]

PhD thesis, 2007

EWD: A metamodeling driven customizable multi-MoC system modeling framework.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2007

Dataflow Architectures for GALS.

[BibT_eX]

[DOI]

Proceedings of the Third International Workshop on Formal Methods for Globally Asynchronous Locally Synchronous Design, 2007

Model Based Test Generation for Microprocessor Architecture Validation.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Assertion-Based Modal Power Estimation.

[BibT_eX]

[DOI]

Proceedings of the Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), 2007

Type Inference for IP Composition.

[BibT_eX]

[DOI]

Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007

Model-driven test generation for system level validation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

A Metamodeling based Framework for Architectural Modeling and Simulator Generation.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2007

Design fault directed test generation for microprocessor validation.

[BibT_eX]

[DOI]

David J. Lilja

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

CARH: service-oriented architecture for validating system-level designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Validating Families of Latency Insensitive Protocols.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2006

A Trace Based Framework for Validation of SoC Designs with GALS Systems.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

SoC Design Space Exploration through Automated IP Selection from SystemC IP Library.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Polychronous Methodology For System Design: A True Concurrency Approach.

[BibT_eX]

[DOI]

Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

MMV: Metamodeling Based Microprocessor Valiation Environment.

[BibT_eX]

[DOI]

David J. Lilja

Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

MCF: A Metamodeling-based Visual Component Composition Framework.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2006

2005

XFM: An incremental methodology for developing formal models.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2005

A Functional Programming Framework for Latency Insensitive Protocol Validation.

[BibT_eX]

[DOI]

Proceedings of the Second Workshop on Globally Asynchronous, Locally Synchronous Design, 2005

System Level Design Methodology for System On Chips using Multi-Threaded Graphs.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Automated Extraction of Structural Information from SystemC-based IP for Validation.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

Modelling Environment for Heterogeneous Systems based on MoCs.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2005

SystemCXML: An Exstensible SystemC Front end Using XML.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2005

2004

Extreme Formal Modeling (XFM) for Hardware Models.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

Effects of property ordering in an incremental formal modeling methodology.

[BibT_eX]

[DOI]

Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

A Functional Programming Framework of Heterogeneous Model of Computation for System Design.

[BibT_eX]

[DOI]

Hiren D. Patel