Deepak Mathaikutty

According to our database1, Deepak Mathaikutty authored at least 40 papers between 2004 and 2019.

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Bibliography

2019
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization.
J. Solid-State Circuits, 2019

2018
Loihi: A Neuromorphic Manycore Processor with On-Chip Learning.
IEEE Micro, 2018

An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2009
SCoPE: Statistical Regression Based Power Models for Co-Processors Power Estimation.
J. Low Power Electronics, 2009

Metamodeling: An Emerging Representation Paradigm for System-Level Design.
IEEE Design & Test of Computers, 2009

Accurate power estimation of hardware co-processors using system level simulation.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Power estimation methodology for a high-level synthesis framework.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Metamodeling-Driven IP Reuse for SoC Integration and Microprocessor Design.
Artech House, ISBN: 978-1-59693-424-5, 2009

2008
A Trace-Based Framework for Verifiable GALS Composition of IPs.
IEEE Trans. VLSI Syst., 2008

MCF: A Metamodeling-Based Component Composition Framework - Composing SystemC IPs for Executable System Models.
IEEE Trans. VLSI Syst., 2008

MMV: A Metamodeling Based Microprocessor Validation Environment.
IEEE Trans. VLSI Syst., 2008

Dataflow Architectures for GALS.
Electr. Notes Theor. Comput. Sci., 2008

Mining metadata for composability of IPs from SystemC IP library.
Design Autom. for Emb. Sys., 2008

SML-Sys: a functional framework with multiple models of computation for modeling heterogeneous system.
Design Autom. for Emb. Sys., 2008

Applying Verification Collaterals for Accurate Power Estimation.
Proceedings of the Ninth International Workshop on Microprocessor Test and Verification, 2008

Formal Transformation of a KPN Specification to a GALS Implementation.
Proceedings of the Forum on specification and Design Languages, 2008

2007
Metamodeling Driven IP Reuse for System-on-chip Integration and Microprocessor Design.
PhD thesis, 2007

EWD: A metamodeling driven customizable multi-MoC system modeling framework.
ACM Trans. Design Autom. Electr. Syst., 2007

Model Based Test Generation for Microprocessor Architecture Validation.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Assertion-Based Modal Power Estimation.
Proceedings of the Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), 2007

Type Inference for IP Composition.
Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007

Model-driven test generation for system level validation.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

A Metamodeling based Framework for Architectural Modeling and Simulator Generation.
Proceedings of the Forum on specification and Design Languages, 2007

Design fault directed test generation for microprocessor validation.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
CARH: service-oriented architecture for validating system-level designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Validating Families of Latency Insensitive Protocols.
IEEE Trans. Computers, 2006

A Functional Programming Framework for Latency Insensitive Protocol Validation.
Electr. Notes Theor. Comput. Sci., 2006

A Trace Based Framework for Validation of SoC Designs with GALS Systems.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

SoC Design Space Exploration through Automated IP Selection from SystemC IP Library.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Polychronous Methodology For System Design: A True Concurrency Approach.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

MMV: Metamodeling Based Microprocessor Valiation Environment.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

MCF: A Metamodeling-based Visual Component Composition Framework.
Proceedings of the Forum on specification and Design Languages, 2006

2005
XFM: An incremental methodology for developing formal models.
ACM Trans. Design Autom. Electr. Syst., 2005

System Level Design Methodology for System On Chips using Multi-Threaded Graphs.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Automated Extraction of Structural Information from SystemC-based IP for Validation.
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

Modelling Environment for Heterogeneous Systems based on MoCs.
Proceedings of the Forum on specification and Design Languages, 2005

SystemCXML: An Exstensible SystemC Front end Using XML.
Proceedings of the Forum on specification and Design Languages, 2005

2004
Extreme Formal Modeling (XFM) for Hardware Models.
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

Effects of property ordering in an incremental formal modeling methodology.
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

A Functional Programming Framework of Heterogeneous Model of Computation for System Design.
Proceedings of the Forum on specification and Design Languages, 2004


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