V. K. Surya

Orcid: 0009-0003-3690-3885

According to our database1, V. K. Surya authored at least 8 papers between 2023 and 2025.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

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Bibliography

2025
Pin Efficient Tri-Level Based Inductive Coupling Transceiver for 3D ICs.
Proceedings of the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, 2025

Energy Efficient Voltage-Mode Simultaneous Bidirectional Transceiver for Serial Links.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

A Replica Driverless Common/Differential Mode Hybrid for Full-Duplex Signaling in Serial Links.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

A Hybrid SST-CML Full Duplex Simultaneous Bi-Directional Signaling Link.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024
Energy Efficient Resistor-Transconductor Hybrid-Based Full-Duplex Transceiver for Serial Link.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2024

Energy Efficient Integrated Summer and Latch-Based DFE With Reduced Tap Loading.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

2023
A High-Speed Charge-Injection based Double Tail Latch for Decision Feedback Equalizer (DFE).
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

A 26 Gb/s Echo-Cancellation Based Simultaneous Bidirectional Transceiver in 65 nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023


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