V. K. Tomar

According to our database1, V. K. Tomar authored at least 12 papers between 2018 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

2023
10T SRAM cell Analysis for improved Read and Write Noise Margin.
Proceedings of the 14th International Conference on Computing Communication and Networking Technologies, 2023

2022
Design of a soft error hardened SRAM cell with improved access time for embedded systems.
Microprocess. Microsystems, April, 2022

Characterization of Stable 12T SRAM with Improved Critical Charge.
J. Circuits Syst. Comput., 2022

Design of Low Leakage 9T SRAM Cell with Improved Performance for Ultra-Low Power Devices.
J. Circuits Syst. Comput., 2022

2021
A Multi-bit Error Upset Immune 12T SRAM Cell for 5G Satellite Communications.
Wirel. Pers. Commun., 2021

A Review on Performance Evaluation of Different Low Power SRAM Cells in Nano-Scale Era.
Wirel. Pers. Commun., 2021

Design of Low Power Half Select Free 10T Static Random-Access Memory Cell.
J. Circuits Syst. Comput., 2021

Design of Low Power with Expanded Noise Margin Subthreshold 12T SRAM Cell for Ultra-Low Power Devices.
J. Circuits Syst. Comput., 2021

Design of 10T SRAM cell with improved read performance and expanded write margin.
IET Circuits Devices Syst., 2021

2020
Design of a Stable Low Power 11-T Static Random Access Memory Cell.
J. Circuits Syst. Comput., 2020

Performance Evaluation of 6T, 7T, 8T, and 9T SRAM cell Topologies at 90 nm Technology Node.
Proceedings of the 11th International Conference on Computing, 2020

2018
Analysis of Cache(SRAM) Memory for Core i™ 7 Processor.
Proceedings of the 9th International Conference on Computing, 2018


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