Ashish Sachdeva

According to our database, Ashish Sachdeva authored at least 16 papers between 2012 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

Unleashing Massive Connectivity with 6G: From Enabling Technologies and Design Principles to AI-Driven Network Intelligence.

Lav Soni, Ashu Taneja, Ashish Sachdeva

J. Circuits Syst. Comput., May, 2026

2025

Plundervolt attack: A novel simulation-based fault injection attack against embedded systems for accelerating dependability analysis process.

Shaminder Kaur, Ashish Sachdeva, J. Chinna Babu

J. Supercomput., October, 2025

A FinFET-Based Low Leakage 10T Static Random Access Memory Cell.

Anandita Srivastav, Usha Tiwari, Sushanta K. Mandal, Ashish Sachdeva

J. Circuits Syst. Comput., March, 2025

One-Sided Schmitt-Trigger-Based Low Power Read Decoupled 11T CNTFET SRAM with Improved Stability.

M. Elangovan, Kulbhushan Sharma, Ashish Sachdeva, Abdolreza Darabi

Circuits Syst. Signal Process., February, 2025

Schmitt Trigger-Based Low Leakage and Half-Select Free Near-Threshold 10T SRAM Architecture.

Appikatla Phani Kumar, Rohit Lorenzo, Erfan Abbasian, Ashish Sachdeva

J. Circuits Syst. Comput., 2025

2024

A Novel Simulation Approach for Fault Injection Mechanism Assessing Dependability of Cybersecurity Attacks.

Shaminder Kaur, Ashish Sachdeva

J. Circuits Syst. Comput., April, 2024

Read Improved and Low Leakage Power CNTFET Based Hybrid 10t SRAM Cell for Low Power Applications.

M. Elangovan, Kulbhushan Sharma, Ashish Sachdeva, Lipika Gupta

Circuits Syst. Signal Process., March, 2024

2023

Low Power Static Random-Access Memory Cell Design for Mobile Opportunistic Networks Sensor Nodes.

Ashish Sachdeva

J. Circuits Syst. Comput., March, 2023

2022

Design of a soft error hardened SRAM cell with improved access time for embedded systems.

V. K. Tomar, Ashish Sachdeva

Microprocess. Microsystems, April, 2022

Characterization of Stable 12T SRAM with Improved Critical Charge.

Ashish Sachdeva, V. K. Tomar

J. Circuits Syst. Comput., 2022

2021

A Multi-bit Error Upset Immune 12T SRAM Cell for 5G Satellite Communications.

Ashish Sachdeva, V. K. Tomar

Wirel. Pers. Commun., 2021

Design of Low Power Half Select Free 10T Static Random-Access Memory Cell.

Ashish Sachdeva, V. K. Tomar

J. Circuits Syst. Comput., 2021

Design of 10T SRAM cell with improved read performance and expanded write margin.

Ashish Sachdeva, V. K. Tomar

IET Circuits Devices Syst., 2021

2020

Design of a Stable Low Power 11-T Static Random Access Memory Cell.

Ashish Sachdeva, V. K. Tomar

J. Circuits Syst. Comput., 2020

2018

The path to equilibrium in sequential and simultaneous games: A mousetracking study.

Isabelle Brocas, Juan D. Carrillo, Ashish Sachdeva

J. Econ. Theory, 2018

2012

Analog Textual Entailment and Spectral Clustering (ATESC) Based Summarization.

Anand Gupta, Manpreet Kathuria, Arjun Singh, Ashish Sachdeva, Shruti Bhati

Proceedings of the Big Data Analytics, First International Conference, 2012