Ashish Sachdeva

According to our database, Ashish Sachdeva authored at least 10 papers between 2012 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Read Improved and Low Leakage Power CNTFET Based Hybrid 10t SRAM Cell for Low Power Applications.

M. Elangovan, Kulbhushan Sharma, Ashish Sachdeva, Lipika Gupta

Circuits Syst. Signal Process., March, 2024

2023

Low Power Static Random-Access Memory Cell Design for Mobile Opportunistic Networks Sensor Nodes.

Ashish Sachdeva

J. Circuits Syst. Comput., March, 2023

2022

Design of a soft error hardened SRAM cell with improved access time for embedded systems.

V. K. Tomar, Ashish Sachdeva

Microprocess. Microsystems, April, 2022

Characterization of Stable 12T SRAM with Improved Critical Charge.

Ashish Sachdeva, V. K. Tomar

J. Circuits Syst. Comput., 2022

2021

A Multi-bit Error Upset Immune 12T SRAM Cell for 5G Satellite Communications.

Ashish Sachdeva, V. K. Tomar

Wirel. Pers. Commun., 2021

Design of Low Power Half Select Free 10T Static Random-Access Memory Cell.

Ashish Sachdeva, V. K. Tomar

J. Circuits Syst. Comput., 2021

Design of 10T SRAM cell with improved read performance and expanded write margin.

Ashish Sachdeva, V. K. Tomar

IET Circuits Devices Syst., 2021

2020

Design of a Stable Low Power 11-T Static Random Access Memory Cell.

Ashish Sachdeva, V. K. Tomar

J. Circuits Syst. Comput., 2020

2018

The path to equilibrium in sequential and simultaneous games: A mousetracking study.

Isabelle Brocas, Juan D. Carrillo, Ashish Sachdeva

J. Econ. Theory, 2018

2012

Analog Textual Entailment and Spectral Clustering (ATESC) Based Summarization.

Anand Gupta, Manpreet Kathuria, Arjun Singh, Ashish Sachdeva, Shruti Bhati

Proceedings of the Big Data Analytics, First International Conference, 2012