Vesa Lahtinen

According to our database1, Vesa Lahtinen authored at least 10 papers between 2000 and 2007.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

2007
Benchmarking mesh and hierarchical bus networks in system-on-chip context.
J. Syst. Archit., 2007

2006
HIBI Communication Network for System-on-Chip.
J. VLSI Signal Process., 2006

System Level Design Experiences and the Need for Standardization.
Proceedings of the International Symposium on System-on-Chip, 2006

Transaction Level Modeling in Communication Engine Design.
Proceedings of the Forum on specification and Design Languages, 2006

2004
HIBI v.2 Communication Network for System-on-Chip.
Proceedings of the Computer Systems: Architectures, 2004

A Communication-Centric Design Flow for HIBI-Based SoCs.
Proceedings of the Computer Systems: Architectures, 2004

2003
Comparison of synthesized bus and crossbar interconnection architectures.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
Interconnection scheme for continuous-media systems-on-a-chip.
Microprocess. Microsystems, 2002

Optimizing finite state machines for system-on-chip communication.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2000
Reuseable interface in multimedia hardware environment.
Proceedings of the 10th European Signal Processing Conference, 2000


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