Erno Salminen

According to our database1, Erno Salminen authored at least 58 papers between 2001 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2015
Resolving parameter reference management in IP-XACT using Kactus2.
Proceedings of the IECON 2015, 2015

2014
Implementation of Multicore communications API.
Proceedings of the 2014 International Symposium on System-on-Chip, 2014

WOKE: A novel workflow model editor.
Proceedings of the 2014 International Symposium on System-on-Chip, 2014

Gamification of System-on-Chip design.
Proceedings of the 2014 International Symposium on System-on-Chip, 2014

Experiences from System-on-Chip design courses.
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014

2013
A scalable, non-interfering, synthesizable Network-on-Chip monitor - Extended version.
Microprocess. Microsystems, 2013

Recommendations for using Simulated Annealing in task mapping.
Des. Autom. Embed. Syst., 2013

Dependency analysis and visualization tool for Kactus2 IP-XACT design framework.
Proceedings of the 2013 International Symposium on System on Chip, 2013

Framework for industrial embedded system product development and management.
Proceedings of the 2013 International Symposium on System on Chip, 2013

Extending IP-XACT to embedded system HW/SW integration.
Proceedings of the 2013 International Symposium on System on Chip, 2013

Teaching system-on-chip design with FPGAs.
Proceedings of the 10th FPGAworld Conference, 2013

2012
MARTE profile extension for modeling dynamic power management of embedded systems.
J. Syst. Archit., 2012

System-on-Chip deployment with MCAPI abstraction and IP-XACT metadata.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Integration of TTA processor tools to Kactus2 IP-XACT design flow.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

2011
Multicore Communications API (MCAPI) implementation on an FPGA multiprocessor.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

TCEMC: A co-design flow for application-specific multicores.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Applying IP-XACT in product data management.
Proceedings of the 2011 International Symposium on System on Chip, 2011

A set of traffic models for Network-on-Chip benchmarking.
Proceedings of the 2011 International Symposium on System on Chip, 2011

Customizable Datapath Integrated Lock Unit.
Proceedings of the 2011 International Symposium on System on Chip, 2011

Kactus2: Environment for Embedded Product Development Using IP-XACT and MCAPI.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
On design and comparison of on-chip networks.
PhD thesis, 2010

2009
Evaluating SoC Network Performance in MPEG-4 Encoder.
J. Signal Process. Syst., 2009

Application modelling and hardware description for network-on-chip benchmarking.
IET Comput. Digit. Tech., 2009

Performance Evaluation of UML2-Modeled Embedded Streaming Applications with System-Level Simulation.
EURASIP J. Embed. Syst., 2009

Parameterizing simulated annealing for distributing Kahn Process Networks on multiprocessor SoCs.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

Evaluating UML2 modeling of IP-XACT objects for automatic MP-SoC integration onto FPGA.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Evaluating the model accuracy in automated design space exploration.
Microprocess. Microsystems, 2008

Distributed bus arbitration algorithm comparison on FPGA-based MPEG-4 multiprocessor system on chip.
IET Comput. Digit. Tech., 2008

On the credibility of load-latency measurement of network-on-chips.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

Evaluation of heterogeneous multiprocessor architectures by energy and performance optimization.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

Real-time execution monitoring on multi-processor system-on-chip.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

2007
Benchmarking mesh and hierarchical bus networks in system-on-chip context.
J. Syst. Archit., 2007

Automated memory-aware application distribution for Multi-processor System-on-Chips.
J. Syst. Archit., 2007

Implementing a WLAN Video Terminal Using UML and Fully Automated Design Flow.
EURASIP J. Embed. Syst., 2007

Evaluating Large System-on-Chip on Multi-FPGA Platform.
Proceedings of the Embedded Computer Systems: Architectures, 2007

Towards Open Network-on-Chip Benchmarks.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

Optimal Subset Mapping And Convergence Evaluation of Mapping Algorithms for Distributing Task Graphs on Multiprocessor SoC.
Proceedings of the International Symposium on System-on-Chip, 2007

Modeling Embedded Software Platforms with a UML Profile.
Proceedings of the Forum on specification and Design Languages, 2007

On network-on-chip comparison.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Evaluating the Model Accuracy in Automated Design Space Exploration.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

IP Integration Overhead Analysis in System-on-Chip Video Encoder.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Instruction Memory Architecture Evaluation on Multiprocessor FPGA MPEG-4 Encoder.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006
HIBI Communication Network for System-on-Chip.
J. VLSI Signal Process., 2006

UML-based multiprocessor SoC design framework.
ACM Trans. Embed. Comput. Syst., 2006

The Impact of Communication on the Scalability of the Data-parallel Video Encoder on MPSoC.
Proceedings of the International Symposium on System-on-Chip, 2006

Parameterizing Simulated Annealing for Distributing Task Graphs on Multiprocessor SoCs.
Proceedings of the International Symposium on System-on-Chip, 2006

Impact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video Encoder.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Configurable multiprocessor platform with RTOS for distributed execution of UML 2.0 designed applications.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
HIBI-based multiprocessor SoC on FPGA.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A Parallel MPEG-4 Encoder for FPGA Based Multiprocessor SoC.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004
HIBI v.2 Communication Network for System-on-Chip.
Proceedings of the Computer Systems: Architectures, 2004

A Communication-Centric Design Flow for HIBI-Based SoCs.
Proceedings of the Computer Systems: Architectures, 2004

Comparison of hardware IP components for system-on-chip.
Proceedings of the 2004 International Symposium on System-on-Chip, 2004

Practical distributed simulation of a network of wireless terminals.
Proceedings of the 2004 International Symposium on System-on-Chip, 2004

2003
Using a communication generator in SoC architecture exploration.
Proceedings of the 2003 International Symposium on System-on-Chip, 2003

Comparison of synthesized bus and crossbar interconnection architectures.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
Parameter optimization tool for enhancing on-chip network performance.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Interfacing multiple processors in a system-on-chip video encoder.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001


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