Victor Arribas

Orcid: 0000-0002-4178-7933

According to our database1, Victor Arribas authored at least 12 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
All You Need Is Fault: Zero-Value Attacks on AES and a New λ-Detection M&M.
IACR Cryptol. ePrint Arch., 2023

2021
LLTI: Low-Latency Threshold Implementations.
IEEE Trans. Inf. Forensics Secur., 2021

2020
Revisiting a Methodology for Efficient CNN Architectures in Profiling Attacks.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

Cryptographic Fault Diagnosis using VerFI.
Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust, 2020

2019
Beyond the Limits: SHA-3 in Just 49 Slices.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Trade-offs in Protecting Keccak Against Combined Side-Channel and Fault Attacks.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2019

2018
M&M: Masks and Macs against Physical Attacks.
IACR Cryptol. ePrint Arch., 2018

VerMI: Verification Tool for Masked Implementations.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Glitch-Resistant Masking Schemes as Countermeasure Against Fault Sensitivity Analysis.
Proceedings of the 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2018

Guards in Action: First-Order SCA Secure Implementations of Ketje Without Additional Randomness.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

CAPA: The Spirit of Beaver Against Physical Attacks.
Proceedings of the Advances in Cryptology - CRYPTO 2018, 2018

2017
Rhythmic Keccak: SCA Security and Low Latency in HW.
IACR Cryptol. ePrint Arch., 2017


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