Thomas De Cnudde

Orcid: 0000-0002-2711-8645

According to our database1, Thomas De Cnudde authored at least 10 papers between 2014 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
Hardware Masking, Revisited.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

Glitch-Resistant Masking Schemes as Countermeasure Against Fault Sensitivity Analysis.
Proceedings of the 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2018

2017
Securing the PRESENT Block Cipher Against Combined Side-Channel Analysis and Fault Attacks.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Several Masked Implementations of the Boyar-Peralta AES S-Box.
IACR Cryptol. ePrint Arch., 2017

2016
Masking AES with d+1 Shares in Hardware.
IACR Cryptol. ePrint Arch., 2016

Does Coupling Affect the Security of Masked Implementations?
IACR Cryptol. ePrint Arch., 2016

More Efficient Private Circuits II through Threshold Implementations.
Proceedings of the 2016 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2016

PRNGs for Masking Applications and Their Mapping to Evolvable Hardware.
Proceedings of the Smart Card Research and Advanced Applications, 2016

2015
Higher-Order Threshold Implementation of the AES S-Box.
Proceedings of the Smart Card Research and Advanced Applications, 2015

2014
Higher-Order Glitch Resistant Implementation of the PRESENT S-Box.
Proceedings of the Cryptography and Information Security in the Balkans, 2014


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