Noriyuki Miura
Orcid: 0000-0002-0072-6114
According to our database1,
Noriyuki Miura
authored at least 107 papers
between 2004 and 2024.
Collaborative distances:
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Bibliography
2024
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024
Edge-Oriented Point Cloud Compression by Moving Object Detection for Realtime Smart Monitoring.
Proceedings of the 21st IEEE Consumer Communications & Networking Conference, 2024
2023
IACR Cryptol. ePrint Arch., 2023
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
DependableHD: A Hyperdimensional Learning Framework for Edge-Oriented Voltage-Scaled Circuits.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
A Hardware Efficient Reservoir Computing System Using Cellular Automata and Ensemble Bloom Filter.
IEICE Trans. Inf. Syst., 2022
Accurate measurement of charge density in nanoscale particles using an aperture optimization of Fourier based phase reconstruction.
Proceedings of the Computational Imaging XX, online, January 15-26, 2022, 2022
DistriHD: A Memory Efficient Distributed Binary Hyperdimensional Computing Architecture for Image Classification.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
Diffusional Side-Channel Leakage From Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE.
IEEE Trans. Inf. Forensics Secur., 2021
Low-cost distance-spoofing attack on FMCW radar and its feasibility study on countermeasure.
J. Cryptogr. Eng., 2021
More Accurate and Robust PRNU-Based Source Camera Identification with 3-Step 3-Class Approach.
Proceedings of the Digital Forensics and Watermarking - 20th International Workshop, 2021
2020
A Random Interrupt Dithering SAR Technique for Secure ADC Against Reference-Charge Side-Channel Attack.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
IEEE Trans. Computers, 2020
Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices.
IEEE J. Solid State Circuits, 2020
A 0.6-V Adaptive Voltage Swing Serial Link Transmitter Using Near Threshold Body Bias Control and Jitter Estimation.
IEICE Trans. Electron., 2020
IEEE Embed. Syst. Lett., 2020
Proceedings of the International Symposium on Information Theory and Its Applications, 2020
2019
Side-channel leakage from sensor-based countermeasures against fault injection attack.
Microelectron. J., 2019
A 0.72pJ/bit 400μm<sup>2</sup> Physical Random Number Generator Utilizing SAR Technique for Secure Implementation on Sensor Nodes.
IEICE Trans. Electron., 2019
Proceedings of the Information Security and Cryptology - 15th International Conference, 2019
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2019
Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019
2018
A Demonstration of a HT-Detection Method Based on Impedance Measurements of the Wiring Around ICs.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Chip-Package-Board Interactive PUF Utilizing Coupled Chaos Oscillators With Inductor.
IEEE J. Solid State Circuits, 2018
A 286 F<sup>2</sup>/Cell Distributed Bulk-Current Sensor and Secure Flush Code Eraser Against Laser Fault Injection Attack on Cryptographic Processor.
IEEE J. Solid State Circuits, 2018
A 286F<sup>2</sup>/cell distributed bulk-current sensor and secure flush code eraser against laser fault injection attack.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
2017
Design Methodology and Validity Verification for a Reactive Countermeasure Against EM Attacks.
J. Cryptol., 2017
A 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter Utilizing Two-Step Transition Inverter Delay Lines in 28 nm CMOS.
IEICE Trans. Electron., 2017
IEICE Electron. Express, 2017
15.8 A permanent digital archive system based on 4F<sup>2</sup> x-point multi-layer metal nano-dot structure.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Exploiting Bitflip Detector for Non-invasive Probing and its Application to Ineffective Fault Analysis.
Proceedings of the 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2017
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
Introduction to the Special Section on the 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC).
IEEE J. Solid State Circuits, 2016
Proceedings of the International SoC Design Conference, 2016
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016
Ring Oscillator under Laser: Potential of PLL-based Countermeasure against Laser Fault Injection.
Proceedings of the 2016 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2016
A 500MHz-BW -52.5dB-THD Voltage-to-Time Converter utilizing a two-step transition inverter.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan.
IEEE J. Solid State Circuits, 2015
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
A DPA/DEMA/LEMA-resistant AES cryptographic processor with supply-current equalizer and micro EM probe sensor.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
IEEE J. Solid State Circuits, 2014
Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage.
IEICE Trans. Electron., 2014
Chip Level Simulation of Substrate Noise Coupling and Interference in RF ICs with CMOS Digital Noise Emulator.
IEICE Trans. Electron., 2014
EM Attack Is Non-Invasive? - Design Methodology and Validity Verification of EM Attack Sensor.
IACR Cryptol. ePrint Arch., 2014
A local EM-analysis attack resistant cryptographic engine with fully-digital oscillator-based tamper-access sensor.
Proceedings of the Symposium on VLSI Circuits, 2014
A passive supply-resonance suppression filter utilizing inductance-enhanced coupled bonding-wire coils.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014
On-Chip Monitoring for In-Place Diagnosis of Undesired Power Domain Problems in IC Chips.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014
An intermittent-driven supply-current equalizer for 11x and 4x power-overhead savings in CPA-resistant 128bit AES cryptographic processor.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
IEEE Micro, 2013
IEEE J. Solid State Circuits, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A 6nW inductive-coupling wake-up transceiver for reducing standby power of non-contact memory card by 500×.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface.
Proceedings of the 2013 IEEE Hot Chips 25 Symposium (HCS), 2013
Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
Proceedings of the 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, 2013
Measurements and simulation of substrate noise coupling in RF ICs with CMOS digital noise emulator.
Proceedings of the 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, 2013
A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched Transmission Line Couplers and Dicode partial-response channel transceivers.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
A 65fJ/b Inter-Chip Inductive-Coupling Data Transceivers Using Charge-Recycling Technique for Low-Power Inter-Chip Communication in 3-D System Integration.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Simultaneous 6-Gb/s Data and 10-mW Power Transmission Using Nested Clover Coils for Noncontact Memory Card.
IEEE J. Solid State Circuits, 2012
Rotary Coding for Power Reduction and S/N Improvement in Inductive-Coupling Data Communication.
IEEE J. Solid State Circuits, 2012
A 0.025-0.45 W 60%-Efficiency Inductive-Coupling Power Transceiver With 5-Bit Dual-Frequency Feedforward Control for Non-Contact Memory Cards.
IEEE J. Solid State Circuits, 2012
6 W/25 mm<sup>2</sup> Wireless Power Transmission for Non-contact Wafer-Level Testing.
IEICE Trans. Electron., 2012
A 1 TB/s 1 pJ/b 6.4 mm<sup>2</sup>/(TB/s) QDR Inductive-Coupling Interface Between 65-nm CMOS Logic and Emulated 100-nm DRAM.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012
A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012
A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processors.
Proceedings of the 2012 IEEE Symposium on Low-Power and High-Speed Chips, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
A 30 Gb/s/Link 2.2 Tb/s/mm <sup>2</sup> Inductively-Coupled Injection-Locking CDR for High-Speed DRAM Interface.
IEEE J. Solid State Circuits, 2011
A 0.55 V 10 fJ/bit Inductive-Coupling Data Link and 0.7 V 135 fJ/Cycle Clock Link With Dual-Coil Transmission Scheme.
IEEE J. Solid State Circuits, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A 2.7Gb/s/mm<sup>2</sup> 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND Flash memory stacking.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking.
IEEE J. Solid State Circuits, 2010
A 2Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-Die NAND-Flash memory stacking.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
An 8Tb/s 1pJ/b 0.8mm<sup>2</sup>/Tb/s QDR inductive-coupling interface between 65nm CMOS GPU and 0.1µm DRAM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
IEEE J. Solid State Circuits, 2009
A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
A 2 Gb/s Bi-Directional Inter-Chip Data Transceiver With Differential Inductors for High Density Inductive Channel Array.
IEEE J. Solid State Circuits, 2008
A 0.14 pJ/b Inductive-Coupling Transceiver With Digitally-Controlled Precise Pulse Shaping.
IEEE J. Solid State Circuits, 2008
IEICE Trans. Electron., 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
IEEE J. Solid State Circuits, 2007
A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link.
IEEE J. Solid State Circuits, 2007
IEICE Trans. Electron., 2007
A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package.
IEEE J. Solid State Circuits, 2006
IEICE Trans. Electron., 2006
Active Crosstalk Cancel for High-Density Inductive Inter-chip Wireless Communication.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2005
Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect.
IEEE J. Solid State Circuits, 2005
2004
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004