Vignesh Balaji

Orcid: 0009-0003-0850-2363

According to our database1, Vignesh Balaji authored at least 13 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2023
Symphony: Orchestrating Sparse and Dense Tensors with Hierarchical Heterogeneous Processing.
ACM Trans. Comput. Syst., 2023

Community-based Matrix Reordering for Sparse Linear Algebra Optimization.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023

2022
Input, Representation, and Access Pattern Guided Cache Locality Optimizations for Graph Analytics.
PhD thesis, 2022

Improving Locality of Irregular Updates with Hardware Assisted Propagation Blocking.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

2021
Neat: Low-Complexity, Efficient On-Chip Cache Coherence.
CoRR, 2021

P-OPT: Practical Optimal Cache Replacement for Graph Analytics.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

2020
Optimizing Graph Processing and Preprocessing with Hardware Assisted Propagation Blocking.
CoRR, 2020

Peacenik: Architecture Support for Not Failing under Fail-Stop Memory Consistency.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
Combining Data Duplication and Graph Reordering to Accelerate Parallel Graph Processing.
Proceedings of the 28th International Symposium on High-Performance Parallel and Distributed Computing, 2019

2018
When is Graph Reordering an Optimization? Studying the Effect of Lightweight Graph Reordering Across Applications and Input Graphs.
Proceedings of the 2018 IEEE International Symposium on Workload Characterization, 2018

2017
Flexible Support for Fast Parallel Commutative Updates.
CoRR, 2017

Intermittent Computing: Challenges and Opportunities.
Proceedings of the 2nd Summit on Advances in Programming Languages, 2017

POSTER: An Architecture and Programming Model for Accelerating Parallel Commutative Computations via Privatization.
Proceedings of the 22nd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2017


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