Vikram Arkalgud Chandrasetty

Orcid: 0000-0002-6675-226X

According to our database1, Vikram Arkalgud Chandrasetty authored at least 9 papers between 2011 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2016
Repeat-accumulate codes for reconciliation in continuous variable quantum key distribution.
Proceedings of the 2016 Australian Communications Theory Workshop, AusCTW 2016, Melbourne, 2016

2015
Resource efficient LDPC decoders for multimedia communication.
Integr., 2015

2014
Memory-efficient quasi-cyclic spatially coupled low-density parity-check and repeat-accumulate codes.
IET Commun., 2014

2013
Memory Efficient Decoders using Spatially Coupled Quasi-Cyclic LDPC Codes
CoRR, 2013

2012
A Highly Flexible LDPC Decoder using Hierarchical Quasi-Cyclic Matrix with Layered Permutation.
J. Networks, 2012

An area efficient LDPC decoder using a reduced complexity min-sum algorithm.
Integr., 2012

2011
VLSI Design - A Practical Guide for FPGA and ASIC Implementations
Springer Briefs in Electrical and Computer Engineering, Springer, ISBN: 978-1-4614-1120-8, 2011

FPGA Implementation of a LDPC Decoder using a Reduced Complexity Message Passing Algorithm.
J. Networks, 2011

A multi-level Hierarchical Quasi-Cyclic matrix for implementation of flexible partially-parallel LDPC decoders.
Proceedings of the 2011 IEEE International Conference on Multimedia and Expo, 2011


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