Vinay Jayaram

Orcid: 0000-0002-8581-4921

According to our database1, Vinay Jayaram authored at least 18 papers between 2006 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
ArmSym: A Virtual Human-Robot Interaction Laboratory for Assistive Robotics.
IEEE Trans. Hum. Mach. Syst., 2021


2019
Tangent space spatial filters for interpretable and efficient Riemannian classification.
CoRR, 2019

Feature extraction from the Hermitian manifold for Brain-Computer Interfaces.
Proceedings of the 2019 9th International IEEE/EMBS Conference on Neural Engineering (NER), 2019

Interpretable Riemannian Classification in Brain-Computer Interfacing.
Proceedings of the 8th Graz Brain-Computer Interface Conference 2019, 2019

2018
A machine learning approach to taking EEG-based brain-computer interfaces out of the lab.
PhD thesis, 2018

MOABB: Trustworthy algorithm benchmarking for BCIs.
CoRR, 2018

2017
Frequency peak features for low-channel classification in motor imagery paradigms.
Proceedings of the 8th International IEEE/EMBS Conference on Neural Engineering, 2017

Bayesian Regression for Artifact correction in Electroencephalography.
Proceedings of the From Vision to Reality, 2017

2016
Transfer Learning in Brain-Computer Interfaces Abstract\uFFFDThe performance of brain-computer interfaces (BCIs) improves with the amount of avail.
IEEE Comput. Intell. Mag., 2016

Multi-task logistic regression in brain-computer interfaces.
Proceedings of the 2016 IEEE International Conference on Systems, Man, and Cybernetics, 2016

2015
Transfer Learning in Brain-Computer Interfaces.
CoRR, 2015

A Cognitive Brain-Computer Interface for Patients with Amyotrophic Lateral Sclerosis.
Proceedings of the 2015 IEEE International Conference on Systems, 2015

Brain-computer interfacing in amyotrophic lateral sclerosis: Implications of a resting-state EEG analysis.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015

2007
Supply Voltage Noise Aware ATPG for Transition Delay Faults.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design.
Proceedings of the 44th Design Automation Conference, 2007

2006
A novel framework for faster-than-at-speed delay test considering IR-drop effects.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Timing-based delay test for screening small delay defects.
Proceedings of the 43rd Design Automation Conference, 2006


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