Vyas Krishnan

According to our database1, Vyas Krishnan authored at least 7 papers between 2006 and 2010.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2010
TABS: Temperature-Aware Layout-Driven Behavioral Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2010

2009
Simultaneous Peak Temperature and Average Power Minimization during Behavioral Synthesis.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

2008
Clock Period Minimization with Iterative Binding Based on Stochastic Wirelength Estimation during High-Level Synthesis.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007
Minimizing wire delays by net-topology aware binding during floorplan- driven high level synthesis.
Proceedings of the IFIP VLSI-SoC 2007, 2007

A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2006
A genetic algorithm for the design space exploration of datapaths during high-level synthesis.
IEEE Trans. Evol. Comput., 2006

Design Space Exploration of RTL Datapaths Using Rent Parameter based Stochastic Wirelength Estimation.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006


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