Srinivas Katkoori
Orcid: 0000-0002-7589-5836
According to our database1,
Srinivas Katkoori
authored at least 146 papers
between 1994 and 2024.
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Bibliography
2024
SN Comput. Sci., January, 2024
2023
Engaged Student Learning with Gamified Labs: A New Approach for Hardware Security Education.
Proceedings of the IEEE International Conference on Teaching, 2023
Effect of the Dual Attention Suppression Attack on the Performance of Self-Driving Car Models - A Preliminary Study.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023
Layer-Wise Filter Thresholding Based CNN Pruning for Efficient IoT Edge Implementations.
Proceedings of the Internet of Things. Advances in Information and Communication Technology, 2023
Empowering Resource-Constrained IoT Edge Devices: A Hybrid Approach for Edge Data Analysis.
Proceedings of the Internet of Things. Advances in Information and Communication Technology, 2023
Simulated Annealing Based Area Optimization of Multilayer Perceptron Hardware for IoT Edge Devices.
Proceedings of the Internet of Things. Advances in Information and Communication Technology, 2023
On Feasibility of Decision Trees for Edge Intelligence in Highly Constrained Internet-of-Things (IoT).
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
2022
ACM J. Emerg. Technol. Comput. Syst., 2022
Peak Prediction Using Multi Layer Perceptron (MLP) for Edge Computing ASICs Targeting Scientific Applications.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
Intersection Movement Assist and Lane Change Assist V2V Warnings with DSRC-based Basic Safety Messages.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
Improving Student Learning in Hardware Security: Project Vision, Overview, and Experiences.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
Simulated Annealing Based Integerization of Hidden Weights for Area-Efficient IoT Edge Intelligence.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
Slow Moving Vehicle, Do Not Pass, and Stationary Vehicle V2V Warnings Based on DSRC Basic Safety Messages.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
Vehicle-to-Infrastructure based Algorithms for Traffic Light Detection, Red Light Violation, and Wrong-Way Entry Applications.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
An Internet of Medical Things (IoMT) Approach for Remote Assessment of Head and Neck Cancer Patients.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
Proceedings of the International Conference on Connected Vehicle and Expo, 2022
State Encoding Based Watermarking of Sequential Circuits Using Hybridized Darwinian Genetic Algorithm.
Behavioral Synthesis for Hardware Security, 2022
Behavioral Synthesis for Hardware Security, 2022
Behavioral Synthesis for Hardware Security, 2022
2021
ACM Trans. Design Autom. Electr. Syst., 2021
Partial evaluation based triple modular redundancy for single event upset mitigation.
Integr., 2021
Enhancing PRESENT-80 and Substitution-Permutation Network Cipher Security with Dynamic "Keyed" Permutation Networks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021
Defending Against Misspeculation-based Cache Probe Attacks Using Variable Record Table.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
ReOPUF: Relaxation Oscillator Physical Unclonable Function for Reliable Key Generation in IoT Security.
Proceedings of the Internet of Things. Technology and Applications, 2021
Proceedings of the Internet of Things. Technology and Applications, 2021
Proceedings of the Internet of Things. Technology and Applications, 2021
2020
Interval Arithmetic and Self-Similarity Based RTL Input Vector Control for Datapath Leakage Minimization.
ACM Trans. Design Autom. Electr. Syst., 2020
Gate Level NBTI and Leakage Co-Optimization in Combinational Circuits with Input Vector Cycling.
IEEE Trans. Emerg. Top. Comput., 2020
IEEE Trans. Dependable Secur. Comput., 2020
SN Comput. Sci., 2020
A Framework for Hardware Trojan Vulnerability Estimation and Localization in RTL Designs.
J. Hardw. Syst. Secur., 2020
Workshops on Extreme Scale Design Automation (ESDA) Challenges and Opportunities for 2025 and Beyond.
CoRR, 2020
Dissecting Convolutional Neural Networks for Efficient Implementation on Constrained Platforms.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Analytical Estimation and Localization of Hardware Trojan Vulnerability in RTL Designs.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
A Distributed Framework for Real Time Object Detection at Low Frame Rates with IoT Edge Nodes.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2020
Novel Bit-Sliced Near-Memory Computing Based VLSI Architecture for Fast Sobel Edge Detection in IoT Edge Devices.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2020
2019
Int. J. Hum. Comput. Stud., 2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
A Darwinian Genetic Algorithm for State Encoding Based Finite State Machine Watermarking.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019
Proceedings of the Internet of Things. A Confluence of Many Disciplines, 2019
Proceedings of the Internet of Things. A Confluence of Many Disciplines, 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
A Survey on Virtual Reality for Individuals with Autism Spectrum Disorder: Design Considerations.
IEEE Trans. Learn. Technol., 2018
ACM Trans. Access. Comput., 2018
Minimizing Performance and Energy Overheads Due to Fanout In Memristor based Logic Implementations.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Optimizing Performance and Energy Overheads Due to Fanout in In-Memory Computing Systems.
Proceedings of the VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, 2018
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
Virtual Reality Interaction Techniques for Individuals with Autism Spectrum Disorder.
Proceedings of the Universal Access in Human-Computer Interaction. Virtual, Augmented, and Intelligent Environments, 2018
An Efficient Hardware-Oriented Runtime Approach for Stack-based Software Buffer Overflow Attacks.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018
Empirical Word-Level Analysis of Arithmetic Module Architectures for Hardware Trojan Susceptibility.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018
2017
Vocational Rehabilitation of Individuals with Autism Spectrum Disorder with Virtual Reality.
ACM Trans. Access. Comput., 2017
LSTM-Based Memory Profiling for Predicting Data Attacks in Distributed Big Data Systems.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017
Proceedings of the Virtual, Augmented and Mixed Reality, 2017
2016
Call Trace and Memory Access Pattern based Runtime Insider Threat Detection for Big Data Platforms.
CoRR, 2016
Vocational training with immersive virtual reality for individuals with autism: towards better design practices.
Proceedings of the 2nd IEEE Workshop on Everyday Virtual Reality, 2016
Proceedings of the Annual IEEE Systems Conference, 2016
Proceedings of the 2016 Symposium on Spatial User Interaction, 2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Virtual Reality Interaction Techniques for Individuals with Autism Spectrum Disorder: Design Considerations and Preliminary Results.
Proceedings of the Human-Computer Interaction. Interaction Platforms and Techniques, 2016
Proceedings of the 2016 Annual Symposium on Computer-Human Interaction in Play, 2016
Effects of Environmental Clutter and Motion on User Performance in Virtual Reality Games.
Proceedings of the Workshop on Fictional Game Elements 2016 co-located with The ACM SIGCHI Annual Symposium on Computer-Human Interaction in Play (CHI PLAY 2016), 2016
Proceedings of the 2016 IEEE International Conference on Big Data (IEEE BigData 2016), 2016
2015
Design and implementation of an embedded system for monitoring at-home solitary Alzheimer's patients.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
2014
Interval Arithmetic and Self Similarity Based Subthreshold Leakage Optimization in RTL Datapaths.
Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
Proceedings of the IEEE International Systems Conference, 2014
2013
A multi-parameter functional side-channel analysis method for hardware trust verification.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
"Scaling" the impact of EDA education Preliminary findings from the CCC workshop series on extreme scale design automation.
Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013
Prototyping of a portable data logging embedded system for naturalistic motorcycle study.
Proceedings of the International Conference on Connected Vehicles and Expo, 2013
2012
Interval arithmetic based input vector control for RTL subthreshold leakage minimization.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 2012
2011
Simultaneous Scheduling, Allocation, Binding, Re-Ordering, and Encoding for Crosstalk Pattern Minimization During High-Level Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2011
State-Retentive Power Gating of Register Files in Multicore Processors Featuring Multithreaded In-Order Cores.
IEEE Trans. Computers, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Customizable FPGA IP Core Implementation of a General-Purpose Genetic Algorithm Engine.
IEEE Trans. Evol. Comput., 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
Simultaneous Peak Temperature and Average Power Minimization during Behavioral Synthesis.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Floorplan Driven High Level Synthesis for Crosstalk Noise Minimization in Macro-cell Based Designs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009
On-chip dynamic worst-case crosstalk pattern detection and elimination for bus-based macro-cell designs.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 27th International Conference on Computer Design, 2009
Proceedings of the 2009 Symposium on Bio-inspired Learning and Intelligent Systems for Security, 2009
2008
Clock Period Minimization with Iterative Binding Based on Stochastic Wirelength Estimation during High-Level Synthesis.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
An Elitist Non-Dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
A customizable FPGA IP core implementation of a general purpose Genetic Algorithm engine.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
Self-Reconfigurable Mixed-Signal Integrated Circuits Architecture Comprising a Field Programmable Analog Array and a General Purpose Genetic Algorithm IP Core.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2008
Bus Binding, Re-ordering, and Encoding for Crosstalk-Producing Switching Activity Minimization during High Level Synthesis.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
Self-Reconfigurable Analog Array Integrated Circuit Architecture for Space Applications.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008
2007
A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Minimizing wire delays by net-topology aware binding during floorplan- driven high level synthesis.
Proceedings of the IFIP VLSI-SoC 2007, 2007
A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the Evolvable Systems: From Biology to Hardware, 2007
2006
A genetic algorithm for the design space exploration of datapaths during high-level synthesis.
IEEE Trans. Evol. Comput., 2006
Design Space Exploration of RTL Datapaths Using Rent Parameter based Stochastic Wirelength Estimation.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006
Self-Adaptive System Based on Field Programmable Gate Array for Extreme Temperature Electronics.
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006
2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Proceedings of the 3rd IEEE International Conference on Pervasive Computing and Communications (PerCom 2005), 2005
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
2004
Net Clustering Based Constructive and Iterative Improvement Approaches for Macro-Cell Placement.
J. VLSI Signal Process., 2004
IEEE Trans. Very Large Scale Integr. Syst., 2004
ACM Trans. Design Autom. Electr. Syst., 2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004
Proceedings of the 2004 Design, 2004
2003
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
IEEE Trans. Very Large Scale Integr. Syst., 2002
An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications.
ACM Trans. Design Autom. Electr. Syst., 2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002
2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1999
RT-level Route-and-Place Design Methodology for Interconnect Optimization in DSM Regime.
Proceedings of the VLSI: Systems on a Chip, 1999
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999
1998
1997
A constructive method for data path area estimation during high-level VLSI synthesis.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
1996
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996
1995
IEEE Des. Test Comput., 1995
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995
1994
Proceedings of the Seventh International Conference on VLSI Design, 1994