Srinivas Katkoori

According to our database1, Srinivas Katkoori authored at least 88 papers between 1994 and 2019.

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Bibliography

2019
Locomotion in virtual reality for room scale tracked areas.
Int. J. Hum.-Comput. Stud., 2019

A Darwinian Genetic Algorithm for State Encoding Based Finite State Machine Watermarking.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

2018
CSRO-Based Reconfigurable True Random Number Generator Using RRAM.
IEEE Trans. VLSI Syst., 2018

A Survey on Virtual Reality for Individuals with Autism Spectrum Disorder: Design Considerations.
TLT, 2018

Effects of Virtual Reality Properties on User Experience of Individuals with Autism.
TACCESS, 2018

Minimizing Performance and Energy Overheads Due to Fanout In Memristor based Logic Implementations.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

High-level synthesis of key based obfuscated RTL datapaths.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Virtual Reality Interaction Techniques for Individuals with Autism Spectrum Disorder.
Proceedings of the Universal Access in Human-Computer Interaction. Virtual, Augmented, and Intelligent Environments, 2018

An Efficient Hardware-Oriented Runtime Approach for Stack-based Software Buffer Overflow Attacks.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018

Empirical Word-Level Analysis of Arithmetic Module Architectures for Hardware Trojan Susceptibility.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018

2017
Vocational Rehabilitation of Individuals with Autism Spectrum Disorder with Virtual Reality.
TACCESS, 2017

LSTM-Based Memory Profiling for Predicting Data Attacks in Distributed Big Data Systems.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

Effects of Instruction Methods on User Experience in Virtual Reality Serious Games.
Proceedings of the Virtual, Augmented and Mixed Reality, 2017

2016
Call Trace and Memory Access Pattern based Runtime Insider Threat Detection for Big Data Platforms.
CoRR, 2016

Vocational training with immersive virtual reality for individuals with autism: towards better design practices.
Proceedings of the 2nd IEEE Workshop on Everyday Virtual Reality, 2016

Embedded system design of a real-time parking guidance system.
Proceedings of the Annual IEEE Systems Conference, 2016

Locomotion in Virtual Reality for Individuals with Autism Spectrum Disorder.
Proceedings of the 2016 Symposium on Spatial User Interaction, 2016

State encoding based NBTI optimization in finite state machines.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Virtual Reality Interaction Techniques for Individuals with Autism Spectrum Disorder: Design Considerations and Preliminary Results.
Proceedings of the Human-Computer Interaction. Interaction Platforms and Techniques, 2016

Point & Teleport Locomotion Technique for Virtual Reality.
Proceedings of the 2016 Annual Symposium on Computer-Human Interaction in Play, 2016

Effects of Environmental Clutter and Motion on User Performance in Virtual Reality Games.
Proceedings of the Workshop on Fictional Game Elements 2016 co-located with The ACM SIGCHI Annual Symposium on Computer-Human Interaction in Play (CHI PLAY 2016), 2016

Memory access pattern based insider threat detection in big data systems.
Proceedings of the 2016 IEEE International Conference on Big Data, 2016

2014
Interval Arithmetic and Self Similarity Based Subthreshold Leakage Optimization in RTL Datapaths.
Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014

Self similarity and interval arithmetic based leakage optimization in RTL datapaths.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Embedded system design of an advanced illumination measurement system for highways.
Proceedings of the IEEE International Systems Conference, 2014

2013
A multi-parameter functional side-channel analysis method for hardware trust verification.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

"Scaling" the impact of EDA education Preliminary findings from the CCC workshop series on extreme scale design automation.
Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013

2012
Interval arithmetic based input vector control for RTL subthreshold leakage minimization.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

A novel method for watermarking sequential circuits.
Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 2012

2011
Simultaneous Scheduling, Allocation, Binding, Re-Ordering, and Encoding for Crosstalk Pattern Minimization During High-Level Synthesis.
IEEE Trans. VLSI Syst., 2011

State-Retentive Power Gating of Register Files in Multicore Processors Featuring Multithreaded In-Order Cores.
IEEE Trans. Computers, 2011

2010
TABS: Temperature-Aware Layout-Driven Behavioral Synthesis.
IEEE Trans. VLSI Syst., 2010

Customizable FPGA IP Core Implementation of a General-Purpose Genetic Algorithm Engine.
IEEE Trans. Evolutionary Computation, 2010

2009
A Framework for Power-Gating Functional Units in Embedded Microprocessors.
IEEE Trans. VLSI Syst., 2009

Simultaneous Peak Temperature and Average Power Minimization during Behavioral Synthesis.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Floorplan Driven High Level Synthesis for Crosstalk Noise Minimization in Macro-cell Based Designs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

On-chip dynamic worst-case crosstalk pattern detection and elimination for bus-based macro-cell designs.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Exploring Compiler Optimizations for Enhancing Power Gating.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Compiler-directed leakage reduction in embedded microprocessors.
Proceedings of the 27th International Conference on Computer Design, 2009

"Glitch Logic" and Applications to Computing and Information Security.
Proceedings of the 2009 Symposium on Bio-inspired Learning and Intelligent Systems for Security, 2009

2008
Clock Period Minimization with Iterative Binding Based on Stochastic Wirelength Estimation during High-Level Synthesis.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

An Elitist Non-Dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Simultaneous Scheduling, Allocation, Binding, Re-ordering, and Encoding for Crosstalk Pattern Minimization during High Level Synthesis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

A customizable FPGA IP core implementation of a general purpose Genetic Algorithm engine.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Self-Reconfigurable Mixed-Signal Integrated Circuits Architecture Comprising a Field Programmable Analog Array and a General Purpose Genetic Algorithm IP Core.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2008

Bus Binding, Re-ordering, and Encoding for Crosstalk-Producing Switching Activity Minimization during High Level Synthesis.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Self-Reconfigurable Analog Array Integrated Circuit Architecture for Space Applications.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008

2007
A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Minimizing wire delays by net-topology aware binding during floorplan- driven high level synthesis.
Proceedings of the IFIP VLSI-SoC 2007, 2007

A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Adaptive and Evolvable Analog Electronics for Space Applications.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2007

2006
A genetic algorithm for the design space exploration of datapaths during high-level synthesis.
IEEE Trans. Evolutionary Computation, 2006

Design Space Exploration of RTL Datapaths Using Rent Parameter based Stochastic Wirelength Estimation.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Temperature-Adaptive Circuits on Reconfigurable Analog Arrays.
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006

Self-Adaptive System Based on Field Programmable Gate Array for Extreme Temperature Electronics.
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006

2005
Intrabus crosstalk estimation using word-level statistics.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Floorplan-Based Crosstalk Estimation for Macrocell-Based Designs.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

System Level Energy Optimization for Location Aware Computing.
Proceedings of the 3rd IEEE International Conference on Pervasive Computing and Communications (PerCom 2005), 2005

Leakage Power Driven Behavioral Synthesis of Pipelined Datapaths.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

2004
Net Clustering Based Constructive and Iterative Improvement Approaches for Macro-Cell Placement.
VLSI Signal Processing, 2004

Ant colony system application to macrocell overlap removal.
IEEE Trans. VLSI Syst., 2004

Power minimization algorithms for LUT-based FPGA technology mapping.
ACM Trans. Design Autom. Electr. Syst., 2004

Intra-Bus Crosstalk Estimation Using Word-Level Statistics.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Ant Colony Optimization Technique for Macrocell Overlap Removal.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Energy Model Based Macrocell Placement for Wirelength Minimization.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Force-Directed Performance-Driven Placement Algorithm for FPGAs.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Tabu Search Based Behavioral Synthesis of Low Leakage Datapaths.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

A Fast Word-Level Statistical Estimator of Intra-Bus Crosstalk.
Proceedings of the 2004 Design, 2004

2003
Resource Allocation and Binding Approach for Low Leakage Power.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

An Architectural Leakage Power Simulator for VHDL Structural Datapaths.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

KnapBind: An Area-Efficient Binding Algorithm for Low-leakage Datapaths.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Efficient LUT-based FPGA technology mapping for power minimization.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Net-based force-directed macrocell placement for wirelength optimization.
IEEE Trans. VLSI Syst., 2002

An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications.
ACM Trans. Design Autom. Electr. Syst., 2002

Net Clustering Based Macrocell Placement.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Force-Directed Scheduling for Dynamic Power Optimization.
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

Behavioral synthesis of datapaths with low leakage power.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Power Optimization of Combinational Circuits by Input Transformations.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

2000
Scheduling for low power under resource and latency constraints.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
RT-level Route-and-Place Design Methodology for Interconnect Optimization in DSM Regime.
Proceedings of the VLSI: Systems on a Chip, 1999

Accurate Resource Estimation Algorithms for Behavioral Synthesis.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998
Architectural Power Estimation Based on Behavior Level Profiling.
VLSI Design, 1998

1997
A constructive method for data path area estimation during high-level VLSI synthesis.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996
A Hierarchical Register Optimization Algorithm for Behavioral Synthesis.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Simulation based architectural power estimation for PLA-based controllers.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1995
Profile-Driven Behavioral Synthesis for Low-Power VLSI Systems.
IEEE Design & Test of Computers, 1995

High level profiling based low power synthesis technique.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

1994
Hierarchical Reconfiguration of VLSI/WSI Arrays.
Proceedings of the Seventh International Conference on VLSI Design, 1994


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