Wang-Dauh Tseng

According to our database, Wang-Dauh Tseng authored at least 21 papers between 1996 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

A Cascaded Multicasting Architecture for Test Data Compression.

Wang-Dauh Tseng

J. Electron. Test., 2021

2019

Multi-Scan Architecture with Scan Chain Disabling Technique for Capture Power Reduction.

Jen-Cheng Ying, Wang-Dauh Tseng, Wen-Jiin Tsai

J. Inf. Sci. Eng., 2019

2018

Asymmetry dual-LFSR reseeding for low power BIST.

Jen-Cheng Ying, Wang-Dauh Tseng, Wen-Jiin Tsai

Integr., 2018

Bipolar Dual-LFSR Reseeding for Low-Power Testing.

Jen-Cheng Ying, Wang-Dauh Tseng, Wen-Jiin Tsai

Proceedings of the IEEE Conference on Dependable and Secure Computing, 2018

2012

$2^{n}$ Pattern Run-Length for Test Data Compression.

Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Cheng-Ho Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Dual-LFSR Reseeding for Low Power Testing.

Lung-Jen Lee, Wang-Dauh Tseng, Wen-Ting Yang

Proceedings of the 13th International Workshop on Microprocessor Test and Verification, 2012

Two-Way Multicasting for Test Data Compression.

Lung-Jen Lee, Wang-Dauh Tseng, Wei-Shun Chen

Proceedings of the 13th International Workshop on Microprocessor Test and Verification, 2012

Deterministic ATPG for Low Capture Power Testing.

Lung-Jen Lee, Chia-Cheng He, Wang-Dauh Tseng

Proceedings of the 13th International Workshop on Microprocessor Test and Verification, 2012

2010

Deterministic built-in self-test using multiple linear feedback shift registers for test power and test volume reduction.

Wang-Dauh Tseng, Lung-Jen Lee, Rung-Bin Lin

IET Comput. Digit. Tech., 2010

Test Data Compression Using Multi-dimensional Pattern Run-length Codes.

Wang-Dauh Tseng, Lung-Jen Lee

J. Electron. Test., 2010

2009

Deterministic Built-In Self-Test Using Multiple Linear Feedback Shift Registers for Low-Power Scan Testing.

Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Chi-Wei Yu

Proceedings of the Eighteentgh Asian Test Symposium, 2009

A Multi-dimensional Pattern Run-Length Method for Test Data Compression.

Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Chen-Lun Lee

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

Power Reduction during Scan Testing Based on Multiple Capture Technique.

Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin

IEICE Trans. Electron., 2008

2007

A novel dynamic Multiple Ring-based Local Restoration for point-to-multipoint multicast traffic in WDM mesh networks.

I-Shyan Hwang, Ren-Yuan Cheng, Wang-Dauh Tseng

Photonic Netw. Commun., 2007

Generation of Primary Input Blocking Pattern for Power Minimization during Scan Testing.

Wang-Dauh Tseng

J. Electron. Test., 2007

Reduction of Power Dissipation during Scan Testing by Test Vector Ordering.

Wang-Dauh Tseng, Lung-Jen Lee

Proceedings of the Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), 2007

2006

A novel dynamic fault restoration mechanism using cluster allocation approach in WDM mesh networks.

I-Shyan Hwang, Meng-Yuan Tu, Wang-Dauh Tseng, Zen-Der Shyu

Comput. Commun., 2006

2002

Printed circuit board routing and package layout codesign.

Shuenn-Shi Chen, Wang-Dauh Tseng, Jin-Tai Yan, Sao-Jie Chen

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

1999

Fuzzy-based CMOS circuit partitioning in built-in current testing.

Wang-Dauh Tseng, Kuochen Wang

IEEE Trans. Very Large Scale Integr. Syst., 1999

1997

Fuzzy-based circuit partitioning in built-in current testing.

Wang-Dauh Tseng, Kuochen Wang

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

Testable Design and Testing of MCMs Based on Multifrequency Scan.

Wang-Dauh Tseng, Kuochen Wang

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996