Wenliang Tseng

According to our database1, Wenliang Tseng authored at least 2 papers between 2001 and 2006.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2006
Passive Reduced-Order Macro-Modeling for Linear Time-Delay Interconnect Systems.
IEICE Trans. Electron., 2006

2001
Configuration free SoC interconnect BIST methodology.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001


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