Wenlong Jiang

According to our database, Wenlong Jiang authored at least 11 papers between 2011 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2024

YOLOv8-FDF: A Small Target Detection Algorithm in Complex Scenes.

Wenlong Jiang, Dezhi Han, Bing Han, Zhongdai Wu

IEEE Access, 2024

Cryptocurrency Transaction Fraud Detection Based on Imbalanced Classification with Interpretable Analysis.

Wenlong Jiang, Pei Yin, Wangwei Zhu

Proceedings of the E-Business. New Challenges and Opportunities for Digital-Enabled Intelligent Future, 2024

Detection of False Data Injection Attacks in Smart Grid Based on Kernel Principal Component Analysis.

Guoqing Zhang, Wengen Gao, Jiaming Zhu, Wenlong Jiang

Proceedings of the 2024 International Conference on Power Electronics and Artificial Intelligence, 2024

2019

A 0.338 cm³, Artifact-Free, 64-Contact Neuromodulation Platform for Simultaneous Stimulation and Sensing.

Dejan Rozgic, Vahagn Hokhikyan, Wenlong Jiang, Ippei Akita, Sina Basir-Kazeruni, Hariprasad Chandrakumar, Dejan Markovic

IEEE Trans. Biomed. Circuits Syst., 2019

Simultaneous Transmission of Up To 94-mW Self-Regulated Wireless Power and Up To 5-Mb/s Reverse Data Over a Single Pair of Coils.

Jiacheng Pan, Asad A. Abidi, Wenlong Jiang, Dejan Markovic

IEEE J. Solid State Circuits, 2019

2018

Self-Regulated Wireless Power and Simultaneous 5MB/S Reverse Data over One Pair of Coils.

Jiacheng Pan, Asad A. Abidi, Wenlong Jiang, Dejan Rozgic, Dejan Markovic

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2017

A ±50-mV Linear-Input-Range VCO-Based Neural-Recording Front-End With Digital Nonlinearity Correction.

Wenlong Jiang, Vahagn Hokhikyan, Hariprasad Chandrakumar, Vaibhav Karkare, Dejan Markovic

IEEE J. Solid State Circuits, 2017

A true full-duplex 32-channel 0.135cm³ neural interface.

Dejan Rozgic, Vahagn Hokhikyan, Wenlong Jiang, Sina Basir-Kazeruni, Hariprasad Chandrakumar, Weiyu Leng, Dejan Markovic

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2016

28.6 A ±50mV linear-input-range VCO-based neural-recording front-end with digital nonlinearity correction.

Wenlong Jiang, Vahagn Hokhikyan, Hariprasad Chandrakumar, Vaibhav Karkare, Dejan Markovic

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2012

Design of ADPLL system for WiMAX applications in 40-nm CMOS.

Wenlong Jiang, Armin Tavakol, Popong Effendrik, Marcel van de Gevel, Frank Verwaal, Robert Bogdan Staszewski

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011

Time-to-digital converter (TDC) for WiMAX ADPLL in 40-nm CMOS.

Popong Effendrik, Wenlong Jiang, Marcel van de Gevel, Frank Verwaal, Robert Bogdan Staszewski

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011