Wenlong Jiang

Orcid: 0000-0003-3029-0769

According to our database1, Wenlong Jiang authored at least 8 papers between 2011 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
A 0.338 cm<sup>3</sup>, Artifact-Free, 64-Contact Neuromodulation Platform for Simultaneous Stimulation and Sensing.
IEEE Trans. Biomed. Circuits Syst., 2019

Simultaneous Transmission of Up To 94-mW Self-Regulated Wireless Power and Up To 5-Mb/s Reverse Data Over a Single Pair of Coils.
IEEE J. Solid State Circuits, 2019

2018
Self-Regulated Wireless Power and Simultaneous 5MB/S Reverse Data over One Pair of Coils.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2017
A ±50-mV Linear-Input-Range VCO-Based Neural-Recording Front-End With Digital Nonlinearity Correction.
IEEE J. Solid State Circuits, 2017

A true full-duplex 32-channel 0.135cm<sup>3</sup> neural interface.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2016
28.6 A ±50mV linear-input-range VCO-based neural-recording front-end with digital nonlinearity correction.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2012
Design of ADPLL system for WiMAX applications in 40-nm CMOS.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
Time-to-digital converter (TDC) for WiMAX ADPLL in 40-nm CMOS.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011


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