Xiang Gao
Affiliations:- Marvell, Santa Clara, CA, USA
- University of Twente, CTIT Research Institute, IC Design Group, Enschede, The Netherlands (former)
According to our database1,
Xiang Gao
authored at least 11 papers
between 2007 and 2015.
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Bibliography
2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2013
Flip-Flops for Accurate Multiphase Clocking: Transmission Gate Versus Current Mode Logic.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector.
IEEE J. Solid State Circuits, 2010
Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
IEEE Trans. Circuits Syst. II Express Briefs, 2009
A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by N<sup>2</sup>.
IEEE J. Solid State Circuits, 2009
A 2.2GHz 7.6mW sub-sampling PLL with -126dBc/Hz in-band phase noise and 0.15psrms jitter in 0.18µm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
Advantages of Shift Registers Over DLLs for Flexible Low Jitter Multiphase Clock Generation.
IEEE Trans. Circuits Syst. II Express Briefs, 2008
2007
Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007