Bram Nauta

According to our database1, Bram Nauta authored at least 196 papers between 2000 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2008, "For contributions to integrated analog circuit design".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2022
Reconstructing Aliased Frequency Spectra by Using Multiple Sample Rates.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Low-Power High-Linearity Mixer-First Receiver Using Implicit Capacitive Stacking With 3× Voltage Gain.
IEEE J. Solid State Circuits, 2022

A 22-nm FDSOI CMOS Low-Noise Active Balun Achieving <sub>p-p</sub> Output Swing Over 0.01-5.4-GHz for Direct RF Sampling Applications.
IEEE J. Solid State Circuits, 2022

A 174μVRMS Input Noise, 1 G8/s Comparator in 22nm FDSOI with a Dynamic-Bias Preamplifier Using Tail Charge Pump and Capacitive Neutralization Across the Latch.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021
Power Efficiency Model for MIMO Transmitters Including Memory Polynomial Digital Predistortion.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

2.4-GHz Highly Selective IoT Receiver Front End With Power Optimized LNTA, Frequency Divider, and Baseband Analog FIR Filter.
IEEE J. Solid State Circuits, 2021

Energy Efficient Startup of Crystal Oscillators Using Stepwise Charging.
IEEE J. Solid State Circuits, 2021

A 0.7-5.7 GHz Reconfigurable MIMO Receiver Architecture for Analog Spatial Notch Filtering Using Orthogonal Beamforming.
IEEE J. Solid State Circuits, 2021

A Single-Trim Frequency Reference Achieving ±120 ppm Accuracy From -50 °C to 170 °C.
IEEE J. Solid State Circuits, 2021

A Baseband-Matching-Resistor Noise-Canceling Receiver With a Three-Stage Inverter-Only OpAmp for High In-Band IIP3 and Wide IF Applications.
IEEE J. Solid State Circuits, 2021

Multi-Receiver Cross-Correlation Technique for (B)FSK Radios.
IEEE Access, 2021

Compensating Processing Delay in Excess of One Clock Cycle in Noise Shaping Loops Without Altering the Filter Topology.
IEEE Access, 2021

2020
Analysis of Switched Capacitor Losses in Polar and Quadrature Switched Capacitor PAs.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Theory and Implementation of a Load-Mismatch Protective Class-E PA System.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

EMI Reduction in Class-D Amplifiers by Actively Reducing PWM Ripple.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Low-Power Highly Selective Channel Filtering Using a Transconductor-Capacitor Analog FIR.
IEEE J. Solid State Circuits, 2020

A Fully Passive RF Front End With 13-dB Gain Exploiting Implicit Capacitive Stacking in a Bottom-Plate N-Path Filter/Mixer.
IEEE J. Solid State Circuits, 2020

EVM-based Performance Evaluation of Co-channel Interference Mitigation using Spatial Filtering for Digital MIMO Receivers.
Proceedings of the 92nd IEEE Vehicular Technology Conference, 2020

30.4 A 370µW 5.5dB-NF BLE/BT5.0/IEEE 802.15.4-Compliant Receiver with >63dB Adjacent Channel Rejection at >2 Channels Offset in 22nm FDSOI.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

A Colpitts-Based Frequency Reference Achieving a Single-Trim ± 120ppm Accuracy from -50 to 170°C.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019
Digital-to-Frequency Converters With a DTC: Theoretical Analysis of the Output SFDR.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A +20 dBm Highly Efficient Linear Outphasing Class-E PA Without AM/AM and AM/PM Characterization Requirements.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Improving Receiver Close-In Blocker Tolerance by Baseband G<sub>m</sub>-C Notch Filtering.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

High-Linearity Bottom-Plate Mixing Technique With Switch Sharing for N-path Filters/Mixers.
IEEE J. Solid State Circuits, 2019

Fast & Energy Efficient Start-Up of Crystal Oscillators by Self-Timed Energy Injection.
IEEE J. Solid State Circuits, 2019

A Self-Oscillating Boosting Amplifier With Adaptive Soft Switching Control for Piezoelectric Transducers.
IEEE J. Solid State Circuits, 2019

A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 0.06-3.4-MHz 92-μW Analog FIR Channel Selection Filter With Very Sharp Transition Band for IoT Receivers.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
Feedforward Phase Noise Cancellation Exploiting a Sub-Sampling Phase Detector.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A Delay Spread Cancelling Waveform Characterizer for RF Power Amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Enhanced-Selectivity High-Linearity Low-Noise Mixer-First Receiver With Complex Pole Pair Due to Capacitive Positive Feedback.
IEEE J. Solid State Circuits, 2018

A 2.4-GHz 16-Phase Sub-Sampling Fractional-N PLL With Robust Soft Loop Switching.
IEEE J. Solid State Circuits, 2018

Outphasing Class-E Power Amplifiers: From Theory to Back-Off Efficiency Improvement.
IEEE J. Solid State Circuits, 2018

A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise.
IEEE J. Solid State Circuits, 2018

Augmentation of Class-E PA Reliability under Load Mismatch Conditions.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
Hardware Implementation Overhead of Switchable Matching Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Beamformer With Constant-Gm Vector Modulators and Its Spatial Intermodulation Distortion.
IEEE J. Solid State Circuits, 2017

24.3 A high-linearity CMOS receiver achieving +44dBm IIP3 and +13dBm B1dB for SAW-less LTE radio.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A 30fJ/comparison dynamic bias comparator.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

An energy reduced sampling technique applied to a 10b 1MS/s SAR ADC.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

Multi-phase sub-sampling fractional-N PLL with soft loop switching for fast robust locking.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

N-path filters and mixer-first receivers: A review.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A digital sine-weighted switched-Gm mixer for single-clock power-scalable parallel receivers.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

Range pre-selection sampling technique to reduce input drive energy for SAR ADCs.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
A 915 MHz 175 µW Receiver Using Transmitted-Reference and Shifted Limiters for 50 dB In-Band Interference Tolerance.
IEEE J. Solid State Circuits, 2016

Introduction to the Special Issue on the 41st European Solid-State Circuits Conference (ESSCIRC).
IEEE J. Solid State Circuits, 2016

26.2 An Ultra-Low-Power receiver using transmitted-reference and shifted limiters for in-band interference resilience.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Random Telegraph Signal phenomena in avalanche mode diodes: Application to SPADs.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

2015
A Sensitive Method to Measure the Integral Nonlinearity of a Digital-to-Time Converter Based on Phase Modulation.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

On the Minimum Number of States for Switchable Matching Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Analysis of the Signal Transfer and Folding in N-Path Filters With a Series Inductance.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

RF Transconductor Linearization Robust to Process, Voltage and Temperature Variations.
IEEE J. Solid State Circuits, 2015

A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging.
IEEE J. Solid State Circuits, 2015

An Interleaved Full Nyquist High-Speed DAC Technique.
IEEE J. Solid State Circuits, 2015

A High-Voltage Class-D Power Amplifier With Switching Frequency Regulation for Improved High-Efficiency Output Power Range.
IEEE J. Solid State Circuits, 2015

Compact Cascadable g m -C All-Pass True Time Delay Cell With Reduced Delay Variation Over Frequency.
IEEE J. Solid State Circuits, 2015

An In-Band Full-Duplex Radio Receiver With a Passive Vector Modulator Downmixer for Self-Interference Cancellation.
IEEE J. Solid State Circuits, 2015

5.5 A forward-body-bias tuned 450MHz Gm-C 3<sup>rd</sup>-order low-pass filter in 28nm UTBB FD-SOI with >1dBVp IIP3 over a 0.7-to-1V supply.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

19.2 A self-interference-cancelling receiver for in-band full-duplex wireless with low distortion under cancellation of strong TX leakage.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

In-band full-duplex transceiver technology for 5G mobile networks.
Proceedings of the ESSCIRC Conference 2015, 2015

Multiphase RF techniques in CMOS: Applied to beam-forming and full duplex receivers: CICC 2015 educational session.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

Sub-sampling PLL techniques.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
A 100-800 MHz 8-Path Polyphase Transmitter With Mixer Duty-Cycle Control Achieving <-40 dBc for ALL Harmonics.
IEEE J. Solid State Circuits, 2014

Comments on "Cancellation of OpAmp Virtual Ground Imperfections by a Negative Conductance Applied to Improve RF Receiver Linearity".
IEEE J. Solid State Circuits, 2014

Cancellation of OpAmp Virtual Ground Imperfections by a Negative Conductance Applied to Improve RF Receiver Linearity.
IEEE J. Solid State Circuits, 2014

Design and Analysis of a High-Efficiency High-Voltage Class-D Power Output Stage.
IEEE J. Solid State Circuits, 2014

A 4-Element Phased-Array System With Simultaneous Spatial- and Frequency-Domain Filtering at the Antenna Inputs.
IEEE J. Solid State Circuits, 2014

Analog/RF Solutions Enabling Compact Full-Duplex Radios.
IEEE J. Sel. Areas Commun., 2014

Towards minimum achievable phase noise of relaxation oscillators.
Int. J. Circuit Theory Appl., 2014

An Ultra Low Energy FSK Receiver With In-Band Interference Robustness Exploiting a Three-Phase Chirped LO.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Software defined radio receivers exploiting noise cancelling: A tutorial review.
IEEE Commun. Mag., 2014

A 110mW, 0.04mm<sup>2</sup>, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist.
Proceedings of the Symposium on VLSI Circuits, 2014

3.5 A 1.0-to-2.5GHz beamforming receiver with constant-Gm vector modulator consuming.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

17.1 An integrated 80V 45W class-D power amplifier with optimal-efficiency-tracking switching frequency regulation.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A 500MHz- 2.7 GHz 8-path weaver downconverter with harmonic rejection and embedded filtering.
Proceedings of the ESSCIRC 2014, 2014

Reconfigurable SDR front-end techniques.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

RF transconductor linearization technique robust to process, voltage and temperature variations.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
Frequency Limitations of First-Order g<sub>m</sub> - RC All-Pass Delay Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

Flip-Flops for Accurate Multiphase Clocking: Transmission Gate Versus Current Mode Logic.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

Tunable N-Path Notch Filters for Blocker Suppression: Modeling and Verification.
IEEE J. Solid State Circuits, 2013

Design of Active N-Path Filters.
IEEE J. Solid State Circuits, 2013

A Flicker Noise/IM3 Cancellation Technique for Active Mixer Using Negative Impedance.
IEEE J. Solid State Circuits, 2013

A Wideband IM3 Cancellation Technique for CMOS Π- and T-Attenuators.
IEEE J. Solid State Circuits, 2013

Spectrum Sensing With High Sensitivity and Interferer Robustness Using Cross-Correlation Energy Detection.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2013

EP1: Antiques from the innovations attic.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

International technical program committee.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Simultaneous spatial and frequency-domain filtering at the antenna inputs achieving up to +10dBm out-of-band/beam P1dB.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A 0.1-to-1.2GHz tunable 6th-order N-path channel-select filter with 0.6dB passband ripple and +7dBm blocker tolerance.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Session 1 overview: Plenary session.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

An integrated 80-V class-D power output stage with 94% efficiency in a 0.14µm SOI BCD process.
Proceedings of the ESSCIRC 2013, 2013

2012
RF Circuit Linearity Optimization Using a General Weak Nonlinearity Model.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A CMOS-Compatible Spectrum Analyzer for Cognitive Radio Exploiting Crosscorrelation to Improve Linearity and Noise Performance.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Active Feedback Technique for RF Channel Selection in Front-End Receivers.
IEEE J. Solid State Circuits, 2012

Widely Tunable 4th Order Switched G<sub>m</sub>-C Band-Pass Filter Based on N-Path Filters.
IEEE J. Solid State Circuits, 2012

Active feedback receiver with integrated tunable RF channel selectivity, distortion cancelling, 48dB stopband rejection and >+12dBm wideband IIP3, occupying <sup>2</sup> in 65nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 1.5-to-5.0GHz input-matched +2dBm P1dB all-passive switched-capacitor beamforming receiver front-end in 65nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 65nm CMOS 1-to-10GHz tunable continuous-time low-pass filter for high-data-rate communications.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

8-Path tunable RF notch filters for blocker suppression.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 1-to-2.5GHz phased-array IC based on gm-RC all-pass time-delay cells.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 0.3-to-1.2GHz tunable 4<sup>th</sup>-order switched gm-C bandpass filter with >55dB ultimate rejection and out-of-band IIP3 of +29dBm.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A wideband IM3 cancellation technique for CMOS attenuators.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Direct-digital modulation (DIDIMO) transmitter with -156dBc/Hz Rx-band noise using FIR structure.
Proceedings of the 38th European Solid-State Circuit conference, 2012

Improving harmonic rejection for spectrum sensing using crosscorrelation.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
Lowering the SNR Wall for Energy Detection Using Cross-Correlation.
IEEE Trans. Veh. Technol., 2011

Noise and Nonlinearity Modeling of Active Mixers for Fast and Accurate Estimation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Spatial Interferer Rejection in a Four-Element Beamforming Receiver Front-End With a Switched-Capacitor Vector Modulator.
IEEE J. Solid State Circuits, 2011

A 65-nm CMOS Temperature-Compensated Mobility-Based Frequency Reference for Wireless Sensor Networks.
IEEE J. Solid State Circuits, 2011

Tunable High-Q N-Path Band-Pass Filters: Modeling and Verification.
IEEE J. Solid State Circuits, 2011

Exploring the Use of Two Antennas for Crosscorrelation Spectrum Sensing.
Proceedings of the 74th IEEE Vehicular Technology Conference, 2011

A 1.0-to-4.0GHz 65nm CMOS four-element beamforming receiver using a switched-capacitor vector modulator with approximate sine weighting via charge redistribution.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Towards suppression of all harmonics in a polyphase multipath transmitter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Jitter-Power minimization of digital frequency synthesis architectures.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Effects of packaging and process spread on a mobility-based frequency reference in 0.16-μm CMOS.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

A narrow-to-wideband scrambling technique increasing software radio receiver linearity.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

2010
Unified Frequency-Domain Analysis of Switched-Series- RC Passive Mixers and Samplers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A 1.2-V 10-μ W NPN-Based Temperature Sensor in 65-nm CMOS With an Inaccuracy of 0.2°C (3 Sigma ) From - 70°C to 125°C.
IEEE J. Solid State Circuits, 2010

A 300-800 MHz Tunable Filter and Linearized LNA Applied in a Low-Noise Harmonic-Rejection RF-Sampling Receiver.
IEEE J. Solid State Circuits, 2010

Discrete-Time Mixing Receiver Architecture for RF-Sampling Software-Defined Radio.
IEEE J. Solid State Circuits, 2010

Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects.
IEEE J. Solid State Circuits, 2010

Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector.
IEEE J. Solid State Circuits, 2010

A 10-bit Charge-Redistribution ADC Consuming 1.9 μ W at 1 MS/s.
IEEE J. Solid State Circuits, 2010

A 200 μA Duty-Cycled PLL for Wireless Sensor Nodes in 65 nm CMOS.
IEEE J. Solid State Circuits, 2010

A 1.2V 10µW NPN-based temperature sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3s) from -70°C to 125°C.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Spur-reduction techniques for PLLs using sub-sampling phase detection.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 2.4GHz 830pJ/bit duty-cycled wake-up receiver with -82dBm sensitivity for crystal-less wireless sensor nodes.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Time delay circuits: A quality criterion for delay variations versus frequency.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Low-Power, High-Speed Transceivers for Network-on-Chip Communication.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

Impulse-Based Scheme for Crystal-Less ULP Radios.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Spurious-Free Dynamic Range of a Uniform Quantizer.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

A Wideband Supply Modulator for 20 MHz RF Bandwidth Polar PAs in 65 nm CMOS.
IEEE J. Solid State Circuits, 2009

A Low-Voltage Mobility-Based Frequency Reference for Crystal-Less ULP Radios.
IEEE J. Solid State Circuits, 2009

Digitally Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference.
IEEE J. Solid State Circuits, 2009

New Associate Editors.
IEEE J. Solid State Circuits, 2009

A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by N<sup>2</sup>.
IEEE J. Solid State Circuits, 2009

A 0.2-to-2.0GHz 65nm CMOS receiver without LNA achieving ≫11dBm IIP3 and ≪6.5 dB NF.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A software-defined radio receiver architecture robust to out-of-band interference.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 400-to-900 MHz receiver with dual-domain harmonic rejection exploiting adaptive interference cancellation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 2.2GHz 7.6mW sub-sampling PLL with -126dBc/Hz in-band phase noise and 0.15psrms jitter in 0.18µm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A sub-1V bandgap voltage reference in 32nm FinFET technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

A 200 µA duty-cycled PLL for wireless sensor nodes.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008
A Two-Stage Approach to Harmonic Rejection Mixing Using Blind Interference Cancellation.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

Theoretical Analysis of Highly Linear Tunable Filters Using Switched-Resistor Techniques.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Advantages of Shift Registers Over DLLs for Flexible Low Jitter Multiphase Clock Generation.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

An Automatic Antenna Tuning System Using Only RF Signal Amplitudes.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

Retraction of Papers With Falsified Information.
IEEE J. Solid State Circuits, 2008

New Associate Editor.
IEEE J. Solid State Circuits, 2008

A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS.
IEEE J. Solid State Circuits, 2008

The Blixer, a Wideband Balun-LNA-I/Q-Mixer Topology.
IEEE J. Solid State Circuits, 2008

Wideband Balun-LNA With Simultaneous Output Balancing, Noise-Canceling and Distortion-Canceling.
IEEE J. Solid State Circuits, 2008

A Discrete-Time Mixing Receiver Architecture with Wideband Harmonic Rejection.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 90μW 12MHz Relaxation Oscillator with a -162dB FOM.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A Wideband Balun LNA I/Q-Mixer combination in 65nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Digital Detection of Oxide Breakdown and Life-Time Extension in Submicron CMOS Technology.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A multi-step P-cell for LNA design automation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A general weak nonlinearity model for LNAs.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Optimal Positions of Twists in Global On-Chip Differential Interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Analytical Design Equations for Class-E Power Amplifiers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Low-Frequency Noise Phenomena in Switched MOSFETs.
IEEE J. Solid State Circuits, 2007

Message from the Incoming Editor-in-Chief.
IEEE J. Solid State Circuits, 2007

Cognitive radios for dynamic spectrum access - polyphase multipath radio circuits for dynamic spectrum access.
IEEE Commun. Mag., 2007

A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 0.28pJ/b 2Gb/s/ch Transceiver in 90nm CMOS for 10mm On-Chip interconnects.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Analog, Mixed-Signal, and RF Circuit Design in Nanometer CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

On the Suitability of Discrete-Time Receivers for Software-Defined Radio.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Multipath Polyphase Circuits and their Application to RF Transceivers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Analytical Design Equations for Class-E Power Amplifiers with Finite DC-Feed Inductance and Switch On-Resistance.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

An inductorless wideband balun-LNA in 65nm CMOS with balanced output.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Jitter requirements of the sampling clock in software radio receivers.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

A Polyphase Multipath Technique for Software-Defined Radio Transmitters.
IEEE J. Solid State Circuits, 2006

Pulse-width modulation pre-emphasis applied in a wireline transmitter, achieving 33 dB loss compensation at 5-Gb/s in 0.13-μm CMOS.
IEEE J. Solid State Circuits, 2006

A 3-Gb/s/ch transceiver for 10-mm uninterrupted RC-limited global on-chip interconnects.
IEEE J. Solid State Circuits, 2006

A multipath technique for canceling harmonics and sidebands in a wideband power upconverter.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Slew rate induced distortion in switched-resistor integrators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Generalized Analytical Design Equations for Variable Slope Class-E Power Amplifiers.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Wireline Equalization using Pulse-Width Modulation.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
Distortion cancellation by polyphase multipath circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Bandwidth of integrated photodiodes in standard CMOS for CD/DVD applications.
Microelectron. Reliab., 2005

A 3-Gb/s optical detector in standard CMOS for 850-nm optical communication.
IEEE J. Solid State Circuits, 2005

Analog circuits in ultra-deep-submicron CMOS.
IEEE J. Solid State Circuits, 2005

Jitter limitations on multi-carrier modulation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
A robust 43-GHz VCO in CMOS for OC-768 SONET applications.
IEEE J. Solid State Circuits, 2004

A CMOS switched transconductor mixer.
IEEE J. Solid State Circuits, 2004

Wide-band CMOS low-noise amplifier exploiting thermal noise canceling.
IEEE J. Solid State Circuits, 2004

A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS.
IEEE J. Solid State Circuits, 2004

Distortion cancellation via polyphase multipath circuits.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Systematic comparison of HF CMOS transconductors.
IEEE Trans. Circuits Syst. II Express Briefs, 2003

2002
Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract).
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

2001
Generating all two-MOS-transistor amplifiers leads to new wide-band LNAs.
IEEE J. Solid State Circuits, 2001

Finding all elementary circuits exploiting transconductance.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
Reducing MOSFET 1/f noise and power consumption by switched biasing.
IEEE J. Solid State Circuits, 2000


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