Mounir Bohsali

According to our database1, Mounir Bohsali authored at least 9 papers between 2007 and 2010.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2010
Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector.
IEEE J. Solid State Circuits, 2010

Spur-reduction techniques for PLLs using sub-sampling phase detection.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by N<sup>2</sup>.
IEEE J. Solid State Circuits, 2009

Device, Circuit, and System Considerations for 60 GHz CMOS.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

A 2.2GHz 7.6mW sub-sampling PLL with -126dBc/Hz in-band phase noise and 0.15psrms jitter in 0.18µm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 10Gb/s NRZ receiver with feedforward equalizer and glitch-free phase-frequency detector.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2007
Millimeter-Wave Devices and Circuit Blocks up to 104 GHz in 90 nm CMOS.
IEEE J. Solid State Circuits, 2007

Low-Power mm-Wave Components up to 104GHz in 90nm CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 60 GHz Power Amplifier in 90nm CMOS Technology.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007


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