Xianwei Cheng

Orcid: 0009-0001-3550-2647

According to our database1, Xianwei Cheng authored at least 11 papers between 2018 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Output-Directed Dynamic Quantization for DNN Acceleration.
Proceedings of the 52nd International Conference on Parallel Processing, 2023

2022
MLCNN: Cross-Layer Cooperative Optimization and Accelerator Architecture for Speeding Up Deep Learning Applications.
Proceedings of the 2022 IEEE International Parallel and Distributed Processing Symposium, 2022

2021
APCNN: Explore Multi-Layer Cooperation for CNN Optimization and Acceleration on FPGA.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

2020
Alleviating Bottlenecks for DNN Execution on GPUs via Opportunistic Computing.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

AMOEBA: a coarse grained reconfigurable architecture for dynamic GPU scaling.
Proceedings of the ICS '20: 2020 International Conference on Supercomputing, 2020

2019
Detection of Occluded Road Signs on Autonomous Driving Vehicles.
Proceedings of the IEEE International Conference on Multimedia and Expo, 2019

Exploration of System Configuration in Effective Training of CNNs on GPGPUs.
Proceedings of the IEEE International Conference on Consumer Electronics, 2019

Improving GPU NoC Power Efficiency through Dynamic Bandwidth Allocation.
Proceedings of the IEEE International Conference on Consumer Electronics, 2019

A Low-Cost and Energy-Efficient NoC Architecture for GPGPUs.
Proceedings of the 2019 ACM/IEEE Symposium on Architectures for Networking and Communications Systems, 2019

2018
Designing Scalable Hybrid Wireless NoC for GPGPUs.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Packet pump: overcoming network bottleneck in on-chip interconnects for GPGPUs.
Proceedings of the 55th Annual Design Automation Conference, 2018


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