Saraju P. Mohanty

According to our database1, Saraju P. Mohanty authored at least 217 papers between 1999 and 2019.

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2019
Toward the Vision of All-Electric Vehicles in a Decade [Energy and Security].
IEEE Consumer Electronics Magazine, 2019

Fog Computing Security Challenges and Future Directions [Energy and Security].
IEEE Consumer Electronics Magazine, 2019

Unmanned Arial Vehicles as Consumer Electronics [Notes from the Editor].
IEEE Consumer Electronics Magazine, 2019

Smart Energy Is the Key for Sustainability [Notes from the Editor].
IEEE Consumer Electronics Magazine, 2019

Consumer Electronics Can Ensure Food Safety [Notes from the Editor].
IEEE Consumer Electronics Magazine, 2019

Unmanned Aerial Vehicles in Consumer Applications: New Applications in Current and Future Smart Environments.
IEEE Consumer Electronics Magazine, 2019

Security and Privacy Issues in Contemporary Consumer Electronics [Energy and Security].
IEEE Consumer Electronics Magazine, 2019

Exploration of System Configuration in Effective Training of CNNs on GPGPUs.
Proceedings of the IEEE International Conference on Consumer Electronics, 2019

Low-Overhead Robust RTL Signature for DSP Core Protection: New Paradigm for Smart CE Design.
Proceedings of the IEEE International Conference on Consumer Electronics, 2019

An IoT-based Drug Delivery System for Refractory Epilepsy.
Proceedings of the IEEE International Conference on Consumer Electronics, 2019

Stress-Log: An IoT-based Smart System to Monitor Stress-Eating.
Proceedings of the IEEE International Conference on Consumer Electronics, 2019

Proof-of-Authentication for Scalable Blockchain in Resource-Constrained Distributed Systems.
Proceedings of the IEEE International Conference on Consumer Electronics, 2019

Improving GPU NoC Power Efficiency through Dynamic Bandwidth Allocation.
Proceedings of the IEEE International Conference on Consumer Electronics, 2019

2018
Smart-Log: A Deep-Learning Based Automated Nutrition Monitoring System in the IoT.
IEEE Trans. Consumer Electronics, 2018

Low-Cost Obfuscated JPEG CODEC IP Core for Secure CE Hardware.
IEEE Trans. Consumer Electronics, 2018

Multi-Phase Obfuscation of Fault Secured DSP Designs With Enhanced Security Feature.
IEEE Trans. Consumer Electronics, 2018

Triple-Phase Watermarking for Reusable IP Core Protection During Architecture Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Guest Editorial Circuit and System Design Automation for Internet of Things.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

A Multiple Input Floating Gate Based Arithmetic Logic Unit with a Feedback Loop for Digital Calibration.
J. Low Power Electronics, 2018

Calibration method to reduce the error in logarithmic conversion with its circuit implementation.
IET Circuits, Devices & Systems, 2018

Secure and Sustainable Load Balancing of Edge Data Centers in Fog Computing.
IEEE Communications Magazine, 2018

iTour: The Future of Smart Tourism: An IoT Framework for the Independent Mobility of Tourists in Smart Cities.
IEEE Consumer Electronics Magazine, 2018

Smart Home Environment for Mild Cognitive Impairment Population: Solutions to Improve Care and Quality of Life.
IEEE Consumer Electronics Magazine, 2018

Everything You Wanted to Know about Smart Health Care: Evaluating the Different Technologies and Components of the Internet of Things for Better Health.
IEEE Consumer Electronics Magazine, 2018

Supercapacitors Outperform Conventional Batteries [Energy and Security].
IEEE Consumer Electronics Magazine, 2018

Building a Sustainable Internet of Things: Energy-Efficient Routing Using Low-Power Sensors Will Meet the Need.
IEEE Consumer Electronics Magazine, 2018

The Blockchain as a Decentralized Security Framework [Future Directions].
IEEE Consumer Electronics Magazine, 2018

Everything You Wanted to Know About the Blockchain: Its Promise, Components, Processes, and Problems.
IEEE Consumer Electronics Magazine, 2018

A Computing Perspective of Quantum Cryptography [Energy and Security].
IEEE Consumer Electronics Magazine, 2018

Quantum Computing in Consumer Electronics [Notes from the Editor].
IEEE Consumer Electronics Magazine, 2018

Consumer Electronics Is the Driver of Smart Cars [Notes from the Editor].
IEEE Consumer Electronics Magazine, 2018

Following the Advent of the Internet, the Blockchain May Revolutionize Consumer Electronics [Notes from the Editor].
IEEE Consumer Electronics Magazine, 2018

Improving the Quality of Life for the Visually Impaired [Notes from the Editor].
IEEE Consumer Electronics Magazine, 2018

Smart Technologies: The Key for Sustainable Smart Cities [Notes from the Editor].
IEEE Consumer Electronics Magazine, 2018

Smart Health Care is Here to Improve Quality of Life [Notes from the Editor].
IEEE Consumer Electronics Magazine, 2018

A Framework for Hardware Efficient Reusable IP Core for Grayscale Image CODEC.
IEEE Access, 2018

SBPG: Secure Better Portable Graphics for Trustworthy Media Communications in the IoT.
IEEE Access, 2018

Designing Scalable Hybrid Wireless NoC for GPGPUs.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Obfuscation of Fault Secured DSP Design Through Hybrid Transformation.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Functional Obfuscation of DSP Cores Using Robust Logic Locking and Encryption.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A Fast and Accurate Approach for Real-Time Seizure Detection in the IoMT.
Proceedings of the IEEE International Smart Cities Conference, 2018

Towards Photonic Sensor based Brain-Computer Interface (BCI).
Proceedings of the IEEE International Smart Cities Conference, 2018

Smart-walk: An intelligent physiological monitoring system for smart families.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

Smart-log: An automated, predictive nutrition monitoring system for infants through the IoT.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

An energy efficient epileptic seizure detector.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

RelBat: A reliable battery system towards the realization of sustainable electronics.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

2017
DSP design protection in CE through algorithmic transformation based structural obfuscation.
IEEE Trans. Consumer Electronics, 2017

TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling With Optimal Loop Unrolling Factor During High Level Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Minimal reversible circuit synthesis on a DNA computer.
Natural Computing, 2017

A new region aware invisible robust blind watermarking approach.
Multimedia Tools Appl., 2017

A novel switchable pin method for regulating power in chip-multiprocessor.
Integration, 2017

Guest editorial - Special issue on hardware assisted techniques for IoT and bigdata applications.
Integration, 2017

Low-cost security aware HLS methodology.
IET Computers & Digital Techniques, 2017

Big-Sensing-Data Curation for the Cloud is Coming: A Promise of Scalable Cloud-Data-Center Mitigation for Next-Generation IoT and Wireless Sensor Networks.
IEEE Consumer Electronics Magazine, 2017

Building Security Perimeters to Protect Network Systems Against Cyber Threats [Future Directions].
IEEE Consumer Electronics Magazine, 2017

Everything You Want to Know About Watermarking: From Paper Marks to Hardware Protection: From paper marks to hardware protection.
IEEE Consumer Electronics Magazine, 2017

Light to Serve as an Effective Wireless Communications Medium [Notes from the Editor].
IEEE Consumer Electronics Magazine, 2017

Information Security and IP Protection Are Increasingly Critical in the Current Global Context [Notes from the Editor].
IEEE Consumer Electronics Magazine, 2017

Deep Learning Can Be Crucial for Smart Consumer Electronics [Notes from the Editor].
IEEE Consumer Electronics Magazine, 2017

IEEE Consumer Electronics Magazine Editorial Board.
IEEE Consumer Electronics Magazine, 2017

Consumer Electronics Can Help Improve Life [Notes from the Editor].
IEEE Consumer Electronics Magazine, 2017

Pay-Cloak: A Biometric Back Cover for Smartphones: Facilitating secure contactless payments and identity virtualization at low cost to end users.
IEEE Consumer Electronics Magazine, 2017

Swing-Pay: One Card Meets All User Payment and Identity Needs: A Digital Card Module using NFC and Biometric Authentication for Peer-to-Peer Payment.
IEEE Consumer Electronics Magazine, 2017

Compact Modeling of Graphene Barristor for Digital Integrated Circuit Design.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Reconfigurable Robust Hybrid Oscillator Arbiter PUF for IoT Security Based on DL-FET.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Dopingless Transistor Based Hybrid Oscillator Arbiter Physical Unclonable Function.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2016
Wireless Sensor Network Simulation Frameworks: A Tutorial Review: MATLAB/Simulink bests the rest.
IEEE Consumer Electronics Magazine, 2016

My First Issue as Editor-in-Chief [Notes from the Editor].
IEEE Consumer Electronics Magazine, 2016

Everything You Wanted to Know About Smart Cities.
IEEE Consumer Electronics Magazine, 2016

IEEE Access Special Section Editorial: Security and Reliability Aware System Design for Mobile Computing Devices.
IEEE Access, 2016

Design of a High-Performance System for Secure Image Communication in the Internet of Things.
IEEE Access, 2016

A Low-Cost Mixed Clock Generator for High Speed Adiabatic Logic.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

STA: A Highly Scalable Low Latency Butterfly Fat Tree Based 3D NoC Design.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Energy-Efficient Design of the Secure Better Portable Graphics Compression Architecture for Trusted Image Communication in the IoT.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Embedding low cost optimal watermark during high level synthesis for reusable IP core protection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A wireless sensor network simulation framework for structural health monitoring in smart cities.
Proceedings of the IEEE 6th International Conference on Consumer Electronics - Berlin, 2016

2015
FuzzRoute: A Thermally Efficient Congestion-Free Global Routing Method for Three-Dimensional Integrated Circuits.
ACM Trans. Design Autom. Electr. Syst., 2015

Guest Editorial: Special Section on Circuit and System Design Methodologies for Emerging Technologies.
IEEE Trans. Emerging Topics Comput., 2015

A nature-inspired firefly algorithm based approach for nanoscale leakage optimal RTL structure.
Integration, 2015

An Algorithm Used in a Power Monitor to Mitigate Dark Silicon on VLSI Chip.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Multi-swarm Optimization of a Graphene FET Based Voltage Controlled Oscillator Circuit.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Simscape Based Ultra-Fast Design Exploration of Graphene-Nanoelectronic Systems.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Ultra-fast variability-aware optimization of mixed-signal designs using bootstrapped kriging.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2014
Fast Design Optimization Through Simple Kriging Metamodeling: A Sense Amplifier Case Study.
IEEE Trans. VLSI Syst., 2014

Nano-CMOS thermal sensor design optimization for efficient temperature measurement.
Integration, 2014

Variability-aware architecture level optimization techniques for robust nanoscale chip design.
Computers & Electrical Engineering, 2014

FuzzRoute: A Method for Thermally Efficient Congestion Free Global Routing in 3D ICs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Exploring Kriging for Fast and Accurate Design Optimization of Nanoscale Analog Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Data Correlation Aware Serial Encoding for Low Switching Power On-Chip Communication.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

A Low Latency Scalable 3D NoC Using BFT Topology with Table Based Uniform Routing.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Kriging bootstrapped neural network training for fast and accurate process variation analysis.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Statistical process variation analysis of a graphene FET based LC-VCO for WLAN applications.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Variability-aware design of double gate FinFET-based current mirrors.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

A performance enhancing hybrid locally mesh globally star NoC topology.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Simscape design flow for memristor based programmable oscillators.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

A Highly Parameterizable Simulator for Performance Analysis of NoC Architectures.
Proceedings of the 2014 International Conference on Information Technology, 2014

2013
Fast optimization of nano-CMOS voltage-controlled oscillator using polynomial regression and genetic algorithm.
Microelectronics Journal, 2013

TSV: A novel energy efficient Memory Integrity Verification scheme for embedded systems.
Journal of Systems Architecture - Embedded Systems Design, 2013

Geostatistical-inspired fast layout optimisation of a nano-CMOS thermal sensor.
IET Circuits, Devices & Systems, 2013

Guest editorial - Design methodologies for nanoelectronic digital and analogue circuits.
IET Circuits, Devices & Systems, 2013

MEM-DnP - A Novel Energy Efficient Approach for Memory Integrity Detection and Protection in Embedded Systems.
CSSP, 2013

Guest Editorial: Advanced Techniques for Efficient Electronic System Design.
CSSP, 2013

Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity.
Computers & Electrical Engineering, 2013

Geostatistics inspired fast layout optimization of nanoscale CMOS phase locked loop.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Fast analog design optimization using regression-based modeling and genetic algorithm: A nano-CMOS VCO case study.
Proceedings of the International Symposium on Quality Electronic Design, 2013

iVAMS: Intelligent metamodel-integrated Verilog-AMS for circuit-accurate system-level mixed-signal design exploration.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012
Enhanced Statistical Blockade Approaches for Fast Robustness Estimation and Compensation of Nano-CMOS Circuits.
J. Low Power Electronics, 2012

A Special Issue on Power, Parasitics, and Process-Variation (P3) Awareness in Mixed-Signal Design.
J. Low Power Electronics, 2012

Accurate Polynomial Metamodeling-Based Ultra-Fast Bee Colony Optimization of a Nano-CMOS Phase-Locked Loop.
J. Low Power Electronics, 2012

Special section on new circuit and architecture-level solutions for multidiscipline systems.
JETC, 2012

Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM.
Integration, 2012

Design of experiments and integer linear programming-assisted conjugate-gradient optimisation of high-κ/metal-gate nano-complementary metal-oxide semiconductor static random access memory.
IET Computers & Digital Techniques, 2012

ISWAR: An Imaging System with Watermarking and Attack Resilience
CoRR, 2012

Kriging-Assisted Ultra-Fast Simulated-Annealing Optimization of a Clamped Bitline Sense Amplifier.
Proceedings of the 25th International Conference on VLSI Design, 2012

Fast-Accurate Non-Polynomial Metamodeling for Nano-CMOS PLL Design Optimization.
Proceedings of the 25th International Conference on VLSI Design, 2012

Metamodel-Assisted Fast and Accurate Optimization of an OP-AMP for Biomedical Applications.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

RAEF: A Power Normalized System-Level Reliability Analysis and Estimation Framework.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

An Investigation of Concurrent Error Detection over Binary Galois Fields in CNTFET and QCA Technologies.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Stochastic Gradient Descent Optimization for Low Power Nano-CMOS Thermal Sensor Design.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Geostatistical-Inspired Metamodeling and Optimization of Nano-CMOS Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Process variation tolerant 9T SRAM bitcell design.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Low complexity cross parity codes for multiple and random bit error correction.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Ordinary Kriging metamodel-assisted Ant Colony algorithm for fast analog design optimization.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Metamodel-assisted ultra-fast memetic optimization of a PLL for WiMax and MMDS applications.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Verilog-AMS-PAM: verilog-AMS integrated with parasitic-aware metamodels for ultra-fast and layout-accurate mixed-signal design exploration.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

STEP: a unified design methodology for secure test and IP core protection.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Particle swarm optimization over non-polynomial metamodels for fast process variation resilient design of Nano-CMOS PLL.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Polynomial-metamodel assisted fast power optimization of Nano-CMOS PLL components.
Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012

Polynomial Metamodel-Based Fast Optimization of Nanoscale PLL Components.
Proceedings of the Models, Methods, and Tools for Complex Chip Design, 2012

2011
A Routing-Aware ILS Design Technique.
IEEE Trans. VLSI Syst., 2011

Real-time perceptual watermarking architectures for video broadcasting.
Journal of Systems and Software, 2011

A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization.
J. Low Power Electronics, 2011

Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

BCH code based multiple bit error correction in finite field multiplier circuits.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Fast optimization of nano-CMOS mixed-signal circuits through accurate metamodeling.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Statistical Blockade Method for Fast Robustness Estimation and Compensation of Nano-CMOS Arithmetic Circuits.
Proceedings of the International Symposium on Electronic System Design, 2011

PVT-tolerant 7-Transistor SRAM Optimization via Polynomial Regression.
Proceedings of the International Symposium on Electronic System Design, 2011

Single-Event Transient Analysis in High Speed Circuits.
Proceedings of the International Symposium on Electronic System Design, 2011

Bee Colony Inspired Metamodeling Based Fast Optimization of a Nano-CMOS PLL.
Proceedings of the International Symposium on Electronic System Design, 2011

Towards robust nano-CMOS sense amplifier design: a dual-threshold versus dual-oxide perspective.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010
DOE-ILP Based Simultaneous Power and Read Stability Optimization in Nano-CMOS SRAM.
J. Low Power Electronics, 2010

ULS: A dual-Vth/high-kappa nano-CMOS universal level shifter for system-level power management.
JETC, 2010

Honeycomb model based skin colour detector for face detection.
IJCAT, 2010

IntellBatt: Toward a Smarter Battery.
IEEE Computer, 2010

A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

A P4VT (Power Performance Process Parasitic Voltage Temperature) Aware Dual-VTh Nano-CMOS VCO.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

On the synthesis of attack tolerant cryptographic hardware.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

On the design of different concurrent EDC schemes for S-Box and GF(p).
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Layout-aware Illinois Scan design for high fault coverage coverage.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Low power nanoscale buffer management for network on chip routers.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009
Design of Parasitic and Process-Variation Aware Nano-CMOS RF Circuits: A VCO Case Study.
IEEE Trans. VLSI Syst., 2009

Impact of gate-oxide tunneling on mixed-signal design and simulation of a nano-CMOS VCO.
Microelectronics Journal, 2009

A secure digital camera architecture for integrated real-time digital rights management.
Journal of Systems Architecture - Embedded Systems Design, 2009

Circuits and systems for real-time security and copyright protection of multimedia.
Computers & Electrical Engineering, 2009

Hardware assisted watermarking for multimedia.
Computers & Electrical Engineering, 2009

Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Unified Challenges in Nano-CMOS High-Level Synthesis.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

ILP based Leakage Optimization during Nano-CMOS RTL Synthesis: A DOXCMOS Versus DTCMOS Perspective.
Proceedings of the World Congress on Nature & Biologically Inspired Computing, 2009

VLSI architectures of perceptual based video watermarking for real-time copyright protection.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

A universal level converter towards the realization of energy efficient implantable drug delivery Nano-Electro-Mechanical-Systems.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

A PVT aware accurate statistical logic library for high- metal-gate nano-CMOS.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Variability-aware optimization of nano-CMOS Active Pixel Sensors using design and analysis of Monte Carlo experiments.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Single ended 6T SRAM with isolated read-port for low-power embedded systems.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Invisible watermarking based on creation and robust insertion-extraction of image adaptive watermarks.
TOMCCAP, 2008

Simultaneous scheduling and binding for low gate leakage nano-complementary metaloxide-semiconductor data path circuit behavioural synthesis.
IET Computers & Digital Techniques, 2008

A single ended 6T SRAM cell design for ultra-low-voltage applications.
IEICE Electronic Express, 2008

Failure analysis for ultra low power nano-CMOS SRAM under process variations.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL Synthesis.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

A Dual Oxide CMOS Universal Voltage Converter for Power Management in Multi-VDD SoCs.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

A nano-CMOS process variation induced read failure tolerant SRAM cell.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

IntellBatt: towards smarter battery design.
Proceedings of the 45th Design Automation Conference, 2008

2007
VLSI architecture and chip for combined invisible robust and fragile watermarking.
IET Computers & Digital Techniques, 2007

Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Metrics to Quantify Steady and Transient Gate Leakage in Nanoscale Transistors: NMOS vs. PMOS Perspective.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006
ILP models for simultaneous energy and transient power minimization during behavioral synthesis.
ACM Trans. Design Autom. Electr. Syst., 2006

A dual voltage-frequency VLSI chip for image watermarking in DCT domain.
IEEE Trans. on Circuits and Systems, 2006

A Page-based Hybrid (Software-Hardware) Dynamic Memory Allocator.
Computer Architecture Letters, 2006

Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

VLSI Architecture for Encryption and Watermarking Units Towards the Making of a Secure Camera.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

A Novel Invisible Color Image Watermarking Scheme Using Image Adaptive Watermark Creation and Robust Insertion-Extraction.
Proceedings of the Eigth IEEE International Symposium on Multimedia (ISM 2006), 2006

Scheduling and binding for low gate leakage nanoCMOS datapath circuit synthesis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Effective tunneling capacitance: a new metric to quantify transient gate leakage current.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

A Congestion Driven Placement Algorithm for FPGA Synthesis.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A High Performance ASIC for Cellular Automata (CA) Applications.
Proceedings of the 9th International Conference in Information Technology, 2006

A Hardware Assisted High Performance PHK Memory Manager.
Proceedings of the ISCA 19th International Conference on Parallel and Distributed Computing Systems, 2006

2005
A VLSI architecture for visible watermarking in a secure still digital camera (S/sup 2/DC) design (Corrected)*.
IEEE Trans. VLSI Syst., 2005

A VLSI architecture for watermarking in a secure still digital camera (S/sup 2/DC) design.
IEEE Trans. VLSI Syst., 2005

Energy-efficient datapath scheduling using multiple voltages and dynamic clocking.
ACM Trans. Design Autom. Electr. Syst., 2005

Simultaneous peak and average power minimization during datapath scheduling.
IEEE Trans. on Circuits and Systems, 2005

Design of a Low Power Image Watermarking Encoder Using Dual Voltage and Frequency.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Reduction of Direct Tunneling Power Dissipation during Behavioral Synthesis of Nanometer CMOS Circuits.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2004
A framework for energy and transient power reduction during behavioral synthesis.
IEEE Trans. VLSI Syst., 2004

VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

FPGA Based Implementation of an Invisible-Robust Image Watermarking Encoder.
Proceedings of the Intelligent Information Technology, 2004

2003
A Framework for Energy and Transient Power Reduction during Behavioral Synthesis.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Energy Efficient Scheduling for Datapath Synthesis.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Peak Power Minimization Through Datapath Scheduling.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

An ILP-based scheduling scheme for energy efficient high performance datapath synthesis.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Transient power minimization through datapath scheduling in multiple supply voltage environment.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Simultaneous peak and average power minimization during datapath scheduling for DSP processors.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

2002
Datapath Scheduling using Dynamic Frequency Clocking.
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

2000
A DCT Domain Visible Watermarking Technique for Images.
Proceedings of the 2000 IEEE International Conference on Multimedia and Expo, 2000

1999
A dual watermarking technique for images.
Proceedings of the 7th ACM International Conference on Multimedia '99, Orlando, FL, USA, October 30, 1999


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