Xiaoping Tang

Proceedings of the 8th International Conference on Information Systems Engineering, 2023

2020

An Assessment of the Relationship between Structural and Functional Imaging of Cerebrovascular Disease and Cognition-Related Fibers.

[BibT_eX]

[DOI]

Comput. Math. Methods Medicine, 2020

2011

Optimal layout decomposition for double patterning technology.

[BibT_eX]

[DOI]

Minsik Cho

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2007

Practical method for obtaining a feasible integer solution in hierarchical layout optimization.

[BibT_eX]

[DOI]

Xin Yuan

Michael S. Gray

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006

Minimizing wire length in floorplanning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Technology migration techniques for simplified layouts with restrictive design rules.

[BibT_eX]

[DOI]

Xin Yuan

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2005

An algorithm for integrated pin assignment and buffer planning.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2005

Optimal redistribution of white space for wire length minimization.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Bus-driven floorplanning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout].

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Tradeoff routing resource, runtime and quality in buffered routing.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

On handling arbitrary rectilinear shape constraint.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Min-cost flow-based algorithm for simultaneous pin assignment and routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

2002

Dummy-feature placement for chemical-mechanical polishinguniformity in a shallow-trench isolation process.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

On mask layout partitioning for electron projection lithography.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

Floorplanning with alignment and performance constraints.

[BibT_eX]

[DOI]

Proceedings of the 39th Design Automation Conference, 2002

2001

Fast evaluation of sequence pair in block placement by longestcommon subsequence computation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Network flow based buffer planning.

[BibT_eX]

[DOI]

Integr., 2001

Dummy feature placement for chemical-mechanical polishing uniformity in a shallow trench isolation process.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Physical Design, 2001

An Algorithm for Simultaneous Pin Assignment and Routing.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

FAST-SP: a fast algorithm for block placement based on sequence pair.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2001, 2001

2000

Planning buffer locations by network flows.

[BibT_eX]

[DOI]

Proceedings of the 2000 International Symposium on Physical Design, 2000

Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation.

[BibT_eX]

[DOI]