Minsik Cho
Orcid: 0000-0003-0481-2682
According to our database1,
Minsik Cho
authored at least 63 papers
between 2005 and 2024.
Collaborative distances:
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Bibliography
2024
eDKM: An Efficient and Accurate Train-Time Weight Clustering for Large Language Models.
IEEE Comput. Archit. Lett., 2024
2023
An RC Delay-Based Pressure-Sensing System With Energy-Efficient Bit-Level Oversampling Techniques for Implantable IOP Monitoring Systems.
IEEE J. Solid State Circuits, October, 2023
CoRR, 2023
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023
Proceedings of the IEEE International Conference on Acoustics, 2023
Proceedings of the IEEE International Conference on Acoustics, 2023
2022
A Continuously-Scalable-Conversion-Ratio Step-Up/Down SC Energy-Harvesting Interface With MPPT Enabled by Real-Time Power Monitoring With Frequency-Mapped Capacitor DAC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Proceedings of the Interspeech 2022, 2022
Proceedings of the Tenth International Conference on Learning Representations, 2022
2021
NASTransfer: Analyzing Architecture Transferability in Large Scale Neural Architecture Search.
Proceedings of the Thirty-Fifth AAAI Conference on Artificial Intelligence, 2021
2020
CoRR, 2020
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020
SNOW: Subscribing to Knowledge via Channel Pooling for Transfer & Lifelong Learning of Convolutional Neural Networks.
Proceedings of the 8th International Conference on Learning Representations, 2020
FlexReduce: Flexible All-reduce for Distributed Deep Learning on Asymmetric Network Topology.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
MUTE: Inter-class Ambiguity Driven Multi-hot Target Encoding for Deep Neural Network Design.
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020
2019
BlueConnect: Decomposing all-reduce for deep learning on heterogeneous network hierarchy.
IBM J. Res. Dev., 2019
CoRR, 2019
CoRR, 2019
Deep Learning for Multi-Messenger Astrophysics: A Gateway for Discovery in the Big Data Era.
CoRR, 2019
BlueConnect: Decomposing All-Reduce for Deep Learning on Heterogeneous Network Hierarchy.
Proceedings of Machine Learning and Systems 2019, 2019
A Unified Approximation Framework for Compressing and Accelerating Deep Neural Networks.
Proceedings of the 31st IEEE International Conference on Tools with Artificial Intelligence, 2019
2018
CoRR, 2018
2017
Proceedings of the 34th International Conference on Machine Learning, 2017
2016
2015
Proc. VLDB Endow., 2015
Proceedings of the IEEE International Conference on Consumer Electronics, 2015
Proceedings of the IEEE International Conference on Consumer Electronics, 2015
2013
Proceedings of the International Symposium on Physical Design, 2013
LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
2012
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
2010
Found. Trends Electron. Des. Autom., 2010
Proceedings of the 2010 International Symposium on Physical Design, 2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Proceedings of the 47th Design Automation Conference, 2010
A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability.
ACM Trans. Design Autom. Electr. Syst., 2009
ELIAD: Efficient Lithography Aware Detailed Routing Algorithm With Compact and Macro Post-OPC Printability Prediction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
2008
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Proceedings of the 2008 International Symposium on Physical Design, 2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction.
Proceedings of the 45th Design Automation Conference, 2008
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Proceedings of the 44th Design Automation Conference, 2007
2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005