Martin D. F. Wong

Proceedings of the 2024 International Symposium on Physical Design, 2024

Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs.

[BibT_eX]

[DOI]

Proceedings of the 2024 International Symposium on Physical Design, 2024

Towards Automated RISC-V Microarchitecture Design with Reinforcement Learning.

[BibT_eX]

[DOI]

Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024

2023

A GPU-Accelerated Framework for Path-Based Timing Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2023

CTM-SRAF: Continuous Transmission Mask-Based Constraint-Aware Subresolution Assist Feature Generation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2023

DRC-SG 2.0: Efficient Design Rule Checking Script Generation via Key Information Extraction.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., September, 2023

Boosting VLSI Design Flow Parameter Tuning with Random Embedding and Multi-objective Trust-region Bayesian Optimization.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., September, 2023

Exploring Rule-Free Layout Decomposition via Deep Reinforcement Learning.

[BibT_eX]

[DOI]

Bentian Jiang

Xinshi Zang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023

GAMER: GPU-Accelerated Maze Routing.

[BibT_eX]

[DOI]

Shiju Lin

Jinwei Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023

LithoBench: Benchmarking AI Computational Lithography for Semiconductor Manufacturing.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023

Multi-Product Optimization for 3D Heterogeneous Integration with D2W Bonding.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

IT-DSE: Invariance Risk Minimized Transfer Microarchitecture Design Space Exploration.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

SPARK: A Scalable Partitioning and Routing Framework for Multi-FPGA Systems.

[BibT_eX]

[DOI]

Xinshi Zang

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

CPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification Systems.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

Fast STA Graph Partitioning Framework for Multi-GPU Acceleration.

[BibT_eX]

[DOI]

Guannan Guo

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Mitigating Distribution Shift for Congestion Optimization in Global Placement.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

On a Moreau Envelope Wirelength Model for Analytical Global Placement.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Physics-Informed Optical Kernel Regression Using Complex-valued Neural Fields.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

OpenILT: An Open Source Inverse Lithography Technique Framework (Invited Paper).

[BibT_eX]

[DOI]

Su Zheng

Bei Yu

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022

Efficient Design Rule Checking Script Generation via Key Information Extraction.

[BibT_eX]

[DOI]

Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

AdaOPC: A Self-Adaptive Mask Optimization Framework for Real Design Patterns.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

ATLAS: A Two-Level Layer-Aware Scheme for Routing with Cell Movement.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

WaferHSL: Wafer Failure Pattern Classification with Efficient Human-Like Staged Learning.

[BibT_eX]

[DOI]

Qijing Wang

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Superfast Full-Scale CPU-Accelerated Global Routing.

[BibT_eX]

[DOI]

Shiju Lin

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

A2-ILT: GPU accelerated ILT with spatial attention mechanism.

[BibT_eX]

[DOI]

Qijing Wang

Bentian Jiang

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Partition and place finite element model on wafer-scale engine.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Xplace: an extremely fast and extensible global placement framework.

[BibT_eX]

[DOI]

Lixin Liu

Bangqi Fu

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

NovelRewrite: node-level parallel AIG rewriting.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

High-Level Synthesis for Minimizing Power Side-Channel Information Leakage.

[BibT_eX]

[DOI]

Wei Ren

Behavioral Synthesis for Hardware Security, 2022

2021

Cpp-Taskflow: A General-Purpose Parallel Task Programming System at Scale.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

OpenTimer v2: A New Parallel Incremental Timing Analysis Engine.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

OpenTimer v2: A Parallel Incremental Timing Analysis Engine.

[BibT_eX]

[DOI]

IEEE Des. Test, 2021

Hotspot Detection via Multi-task Learning and Transformer Encoder.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

TopoPart: a Multi-level Topology-Driven Partitioning Framework for Multi-FPGA Systems.

[BibT_eX]

[DOI]

Dan Zheng

Xinshi Zang

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Starfish: An Efficient P&R Co-Optimization Engine with A*-based Partial Rerouting.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

GAMER: GPU Accelerated Maze Routing.

[BibT_eX]

[DOI]

Shiju Lin

Jinwei Liu

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

GPU-accelerated Critical Path Generation with Path Constraints.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

GPU-accelerated Path-based Timing Analysis.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

On Coloring Rectangular and Diagonal Grid Graphs for Multipatterning and DSA Lithography.

[BibT_eX]

[DOI]

Daifeng Guo

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

An Efficient Work-Stealing Scheduler for Task Dependency Graph.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Conference on Parallel and Distributed Systems, 2020

Learn to Floorplan through Acquisition of Effective Local Search Heuristics.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

An Efficient Critical Path Generation Algorithm Considering Extensive Path Constraints.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

DtCraft: A High-Performance Distributed Execution Engine at Scale.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

A Modern C++ Parallel Task Programming Library.

[BibT_eX]

[DOI]

Proceedings of the 27th ACM International Conference on Multimedia, 2019

Cpp-Taskflow: Fast Task-Based Parallel Programming Using Modern C++.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Parallel and Distributed Processing Symposium, 2019

An Efficient and Composable Parallel Task Programming Library.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE High Performance Extreme Computing Conference, 2019

Distributed Timing Analysis at Scale.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Essential Building Blocks for Creating an Open-source EDA Project.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

A General-purpose Distributed Programming System using Data-parallel Streams.

[BibT_eX]

[DOI]

Proceedings of the 2018 ACM Multimedia Conference on Multimedia Conference, 2018

Accurate Models for Optimizing Tapered Microchannel Heat Sinks in 3D ICs.

[BibT_eX]

[DOI]

Leslie Hwang

Beomjin Kwon

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Routing at compile time.

[BibT_eX]

[DOI]

Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

A Distributed Power Grid Analysis Framework from Sequential Stream Graph.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

MtDetector: A High-performance Marine Traffic Detector at Stream Scale.

[BibT_eX]

[DOI]

Proceedings of the 12th ACM International Conference on Distributed and Event-based Systems, 2018

Accelerate analytical placement with GPU: A generic approach.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

A highly compressed timing macro-modeling algorithm for hierarchical and incremental timing analysis.

[BibT_eX]

[DOI]

Tin-Yin Lai

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

On coloring rectangular and diagonal grid graphs for multiple patterning lithography.

[BibT_eX]

[DOI]

Daifeng Guo

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

DtCraft: A distributed execution engine for compute-intensive applications.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

LibAbs: An Efficient and Accurate Timing Macro-Modeling Algorithm for Large Hierarchical Designs.

[BibT_eX]

[DOI]

Tin-Yin Lai

Proceedings of the 54th Annual Design Automation Conference, 2017

High-Level Synthesis for side-channel defense.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

2016

Circuit Partitioning: A Network-Flow-Based Balanced Min-Cut Approach.

[BibT_eX]

[DOI]

Encyclopedia of Algorithms, 2016

Layout Decomposition for Multiple Patterning.

[BibT_eX]

[DOI]

Haitong Tian

Sven Tenzing Choden Konigsmark

Encyclopedia of Algorithms, 2016

PolyPUF: Physically Secure Self-Divergence.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

UI-Timer 1.0: An Ultrafast Path-Based Timing Analysis Algorithm for CPPR.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Performance evaluation considering mask misalignment in multiple patterning decomposition.

[BibT_eX]

[DOI]

Haitong Tian

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Early Days of Automatic Floorplan Design.

[BibT_eX]

[DOI]

Proceedings of the 2016 on International Symposium on Physical Design, 2016

Information dispersion for trojan defense through high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

A distributed timing analysis framework for large designs.

[BibT_eX]

[DOI]

Natesan Venkateswaran

Proceedings of the 53rd Annual Design Automation Conference, 2016

Contact layer decomposition to enable DSA with multi-patterning technique for standard cell based layout.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Accelerating aerial image simulation using improved CPU/GPU collaborative computing.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2015

On fast timing closure: speeding up incremental path-based timing analysis with mapreduce.

[BibT_eX]

[DOI]

Proceedings of the 2015 ACM/IEEE International Workshop on System Level Interconnect Prediction, 2015

Early Days of Circuit Placement.

[BibT_eX]

[DOI]

Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

Accelerated Path-Based Timing Analysis with MapReduce.

[BibT_eX]

[DOI]

Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

OpenTimer: A High-Performance Timing Analysis Tool.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Layout optimization and template pattern verification for directed self-assembly (DSA).

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

Contact pitch and location prediction for Directed Self-Assembly template verification.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

An efficient linear time triple patterning solver.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Polynomial time optimal algorithm for stencil row planning in e-beam lithography.

[BibT_eX]

[DOI]

Daifeng Guo

Yuelin Du

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

UI-route: An ultra-fast incremental maze routing algorithm.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2014

Triple patterning aware detailed placement with constrained pattern assignment.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

UI-timer: an ultra-fast clock network pessimism removal algorithm.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Fast path-based timing analysis for CPPR.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Optimization of standard cell based detailed placement for 16 nm FinFET process.

[BibT_eX]

[DOI]

Yuelin Du

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Directed Self-Assembly (DSA) Template Pattern Verification.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

On Timing Closure: Buffer Insertion for Hold-Violation Removal.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

System-of-PUFs: Multilevel security for embedded systems.

[BibT_eX]

[DOI]

Leslie K. Hwang

Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

Efficient simulation-based optimization of power grid with on-chip voltage regulator.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

CNPUF: A Carbon Nanotube-based Physically Unclonable Function for secure low-energy hardware design.

[BibT_eX]

[DOI]

Leslie Hwang

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

A routing algorithm for graphene nanoribbon circuit.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2013

A Polynomial Time Exact Algorithm for Overlay-Resistant Self-Aligned Double Patterning (SADP) Layout Decomposition.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

A novel and efficient method for power pad placement optimization.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Quality Electronic Design, 2013

Advances in wire routing.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Quality Electronic Design, 2013

Optimally minimizing overlay violation in self-aligned double patterning decomposition for row-based standard cell layout in polynomial time.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Efficient aerial image simulation on multi-core SIMD CPU.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Constrained pattern assignment for standard cell based triple patterning lithography.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Block copolymer directed self-assembly (DSA) aware contact layer optimization for 10 nm 1D standard cell library.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Spacer-is-dielectric-compliant detailed routing for self-aligned double patterning lithography.

[BibT_eX]

[DOI]

Alexander Miloslavsky

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Network flow modeling for escape routing on staggered pin arrays.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

An ILP-based automatic bus planner for dense PCBs.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Linear time algorithm to find all relocation positions for EUV defect mitigation.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

The nature of optimization problem challenges in physical synthesis.

[BibT_eX]

[DOI]

Ismail Bustany

Igor L. Markov

Proceedings of the American Control Conference, 2013

2012

Correctly Model the Diagonal Capacity in Escape Routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

NP-Completeness and an Approximation Algorithm for Rectangle Escape Problem With Application to PCB Routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Advances in PCB Routing.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2012

A Practical Low-Power Nonregular Interconnect Design With Manufacturing for Design Approach.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

Impact of lithography retargeting process on low level interconnect in 20nm technology.

[BibT_eX]

[DOI]

Proceedings of the International Workshop on System Level Interconnect Prediction, 2012

Algorithmic study on the routing reliability problem.

[BibT_eX]

[DOI]

Zigang Xiao

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Thermal via structural design in three-dimensional integrated circuits.

[BibT_eX]

[DOI]

Leslie Hwang

Kevin L. Lin

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

A polynomial time exact algorithm for self-aligned double patterning layout decomposition.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2012

On simulated annealing in EDA.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2012

Layout small-angle rotation and shift for EUV defect mitigation.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Efficient parallel power grid analysis via Additive Schwarz Method.

[BibT_eX]

[DOI]

Zigang Xiao

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

PGT_SOLVER: An efficient solver for power grid transient analysis.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

A polynomial time triple patterning algorithm for cell based row-structure layout.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technology.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Efficient pattern relocation for EUV blank defect mitigation.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Parallel implementation of R-trees on the GPU.

[BibT_eX]

[DOI]

Lance Leong

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Hybrid lithography optimization with E-Beam and immersion processes for 16nm 1D gridded design.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

A New Strategy for Simultaneous Escape Based on Boundary Routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Thermal-Driven Analog Placement Considering Device Matching.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Lithography-aware layout modification considering performance impact.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Accelerating aerial image simulation with GPU.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Self-aligned double patterning decomposition for overlay minimization and hot spot detection.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

An optimal algorithm for layer assignment of bus escape routing on PCBs.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

Mask cost reduction with circuit performance consideration for self-aligned double patterning.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Routing with graphene nanoribbons.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

A provably good approximation algorithm for Rectangle Escape Problem with application to PCB routing.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

A Routing Approach to Reduce Glitches in Low Power FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Advances in PCB routing.

[BibT_eX]

[DOI]

Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010

Fast block-iterative domain decomposition algorithm for IR drop analysis in large power grid.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

A negotiated congestion based router for simultaneous escape routing.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

B-escape: a simultaneous escape routing algorithm based on boundary routing.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on Physical Design, 2010

BDD-based circuit restructuring for reducing dynamic power.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Computer Design, 2010

On the escape routing of differential pairs.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Recent research development in PCB layout.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

An effective GPU implementation of breadth-first search.

[BibT_eX]

[DOI]

Wen-mei W. Hwu

Proceedings of the 47th Design Automation Conference, 2010

An optimal algorithm for finding disjoint rectangles and its application to PCB routing.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

On process-aware 1-D standard cell design.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Configurable multi-product floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Optimal simultaneous pin assignment and escape routing for dense PCBs.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Dynamic power estimation for deep submicron circuits with process variation.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Theories and algorithms on single-detour routing for untangling twisted bus.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

BSG-Route: A Length-Constrained Routing Scheme for General Planar Topology.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Incremental Improvement of Voltage Assignment.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Archer: A History-Based Global Routing Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Wire shaping is practical.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Symposium on Physical Design, 2009

Optimal layer assignment for escape routing of buses.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

A correct network flow model for escape routing.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

Automatic bus planner for dense PCBs.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

Flip-chip routing with unified area-I/O pad assignments for package-board co-design.

[BibT_eX]

[DOI]

Jia-Wei Fang

Proceedings of the 46th Design Automation Conference, 2009

On using SAT to ordered escape problems.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Slicing Floorplans.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Global Routing Formulation and Maze Routing.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Circuit Partitioning: A Network-Flow-Based Balanced Min-Cut Approach.

[BibT_eX]

[DOI]

Proceedings of the Encyclopedia of Algorithms - 2008 Edition, 2008

Postplacement voltage assignment under performance constraints.

[BibT_eX]

[DOI]

Wilsin Gosti

ACM Trans. Design Autom. Electr. Syst., 2008

Optimal routing algorithms for rectilinear pin clusters in high-density multichip modules.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2008

A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2008

Fast Dummy-Fill Density Analysis With Coupling Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Simultaneous Escape-Routing Algorithms for Via Minimization of High-Speed Boards.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

DDBDD: Delay-Driven BDD Synthesis for FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Thermal-Aware IR Drop Analysis in Large Power Grid.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

BSG-Route: a length-matching router for general topology.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Efficient ASIP design for configurable processors with fine-grained resource sharing.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

Ordered escape routing based on Boolean satisfiability.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Placement-Proximity-Based Voltage Island Grouping Under Performance Requirement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

OPC-Friendly Bus Driven Floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Dummy fill density analysis with coupling constraints.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Symposium on Physical Design, 2007

Is your layout density verification exact?: a fast exact algorithm for density calculation.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Symposium on Physical Design, 2007

Untangling twisted nets for bus routing.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Archer: a history-driven global routing algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Optimal bus sequencing for escape routing in dense PCBs.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Improving Voltage Assignment by Outlier Detection and Incremental Placement.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

Efficient Second-Order Iterative Methods for IR Drop Analysis in Power Grid.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Fast Placement Optimization of Power Supply Pads.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Fast and Accurate OPC for Standard-Cell Layouts.

[BibT_eX]

[DOI]

David M. Pawlowski

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Coupling-aware Dummy Metal Insertion for Lithography.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Two-layer bus routing for high-speed printed circuit boards.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2006

An ECO routing algorithm for eliminating coupling-capacitance violations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Minimizing wire length in floorplanning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

A Length-Matching Routing Algorithm for High-Performance Printed Circuit Boards.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Algorithms for simultaneous escape routing and Layer assignment of dense PCBs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Algorithmic study of single-layer bus routing for high-speed boards.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Floorplan Design for Multimillion Gate FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design.

[BibT_eX]

[DOI]

Hung-Ming Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Temperature-Aware Placement for SOCs.

[BibT_eX]

[DOI]

Jeng-Liang Tsai

Charlie Chung-Ping Chen

Proc. IEEE, 2006

Timing-constrained and voltage-island-aware voltage assignment.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

Closed form solution for optimal buffer sizing using the Weierstrass elliptic function.

[BibT_eX]

[DOI]

Sebastian Vogel

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

An exact algorithm for the statistical shortest path problem.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

An algorithm for integrated pin assignment and buffer planning.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2005

Simultaneous power supply planning and noise avoidance in floorplan design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

IR Drop and Ground Bounce Awareness Timing Model.

[BibT_eX]

[DOI]

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Wire Planning with Bounded Over-the-Block Wires.

[BibT_eX]

[DOI]

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer.

[BibT_eX]

[DOI]

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Current Calculation on VLSI Signal Interconnects.

[BibT_eX]

[DOI]

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Fast algorithms for IR drop analysis in large power grid.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Post-placement voltage island generation under performance requirement.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Optimal routing algorithms for pin clusters in high-density multichip modules.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

An escape routing framework for dense boards with high-speed design constraints.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Buffer insertion under process variations for delay minimization.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Energy optimization in memory address bus structure for application-specific systems.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

CMP aware shuttle mask floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Redundant-via enhanced maze routing for yield improvement.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Optimal redistribution of white space for wire length minimization.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Crowdedness-balanced multilevel partitioning for uniform resource utilization.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Floorplanning for 3-D VLSI design.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Bus-driven floorplanning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout].

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

An ECO algorithm for eliminating crosstalk violations.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on Physical Design, 2004

Rectilinear Steiner Tree Construction Using Answer Set Programming.

[BibT_eX]

[DOI]

Esra Erdem

Proceedings of the Logic Programming, 20th International Conference, 2004

Reticle Floorplanning with Guaranteed Yield for Multi-Project Wafers.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

A Two-Layer Bus Routing Algorithm for High-Speed Boards.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

A provably good algorithm for high performance bus routing.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Simultaneous escape routing and layer assignment for dense PCBs.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Floorplan design for multi-million gate FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Optimal Algorithm for Minimizing the Number of Twists in an On-Chip Bus.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Optical proximity correction (OPC): friendly maze routing.

[BibT_eX]

[DOI]

Li-Da Huang

Proceedings of the 41th Design Automation Conference, 2004

Tradeoff routing resource, runtime and quality in buffered routing.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

On handling arbitrary rectilinear shape constraint.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Analysis of FPGA/FPIC switch modules.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2003

Min-cost flow-based algorithm for simultaneous pin assignment and routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Timing-driven routing for FPGAs based on Lagrangian relaxation.

[BibT_eX]

[DOI]

Seokjin Lee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Maze routing with buffer insertion under transition time constraints.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Design hierarchy-guided multilevel circuit partitioning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Explicit gate delay model for timing evaluation.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Physical Design, 2003

Length-Matching Routing for High-Speed Printed Circuit Boards.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

A Min-Cost Flow Based Detailed Router for FPGAs.

[BibT_eX]

[DOI]

Seokjin Lee

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Stable Multiway Circuit Partitioning for ECO.

[BibT_eX]

[DOI]

Seokjin Lee

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Wire type assignment for FPGA routing.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

Global Wire Bus Configuration with Minimum Delay Uncertainty.

[BibT_eX]

[DOI]

Li-Da Huang

Hung-Ming Chen

Proceedings of the 2003 Design, 2003

Blade and razor: cell and interconnect delay analysis using current-based models.

[BibT_eX]

[DOI]

John F. Croix

Proceedings of the 40th Design Automation Conference, 2003

A fast and accurate method for interconnect current calculation.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Floorplanning with power supply noise avoidance.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation.

[BibT_eX]

[DOI]

Yu-Min Lee

Charlie Chung-Ping Chen

VLSI Design, 2002

Dummy-feature placement for chemical-mechanical polishinguniformity in a shallow-trench isolation process.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Maze routing with buffer insertion and wiresizing.

[BibT_eX]

[DOI]

Minghorng Lai

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

ECO algorithms for removing overlaps between power rails and signal wires.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

On mask layout partitioning for electron projection lithography.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Shaping interconnect for uniform current density.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Incremental reconfiguration of multi-FPGA systems.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002

A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

Floorplanning with alignment and performance constraints.

[BibT_eX]

[DOI]

Proceedings of the 39th Design Automation Conference, 2002

2001

Closed form solutions to simultaneous buffer insertion/sizing and wire sizing.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2001

On extending slicing floorplan to handle L/T-shaped modules andabutment constraints.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Model-based dummy feature placement for oxide chemical-mechanicalpolishing manufacturability.

[BibT_eX]

[DOI]

Robert Boone

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Fast evaluation of sequence pair in block placement by longestcommon subsequence computation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Matching-based algorithm for FPGA channel segmentation design.

[BibT_eX]

[DOI]

Jai-Ming Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Network flow based buffer planning.

[BibT_eX]

[DOI]

Integr., 2001

VLSI Circuit Performance Optimization by Geometric Programming.

[BibT_eX]

[DOI]

Ann. Oper. Res., 2001

Dummy feature placement for chemical-mechanical polishing uniformity in a shallow trench isolation process.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Physical Design, 2001

An Algorithm for Simultaneous Pin Assignment and Routing.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Faster and more accurate wiring evaluation in interconnect-centric floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

LRoute: a delay minimal router for hierarchical CPLDs.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2001

Slicing tree is a complete floorplan representation.

[BibT_eX]

[DOI]

Minghorng Lai

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

A graph based algorithm for optimal buffer insertion under accurate delay models.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

FAST-SP: a fast algorithm for block placement based on sequence pair.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2001, 2001

Integrated power supply planning and floorplanning.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2001, 2001

Memory-efficient interconnect optimization.

[BibT_eX]

[DOI]

Minghorng Lai

Proceedings of ASP-DAC 2001, 2001

A fast and accurate delay estimation method for buffered interconnects.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2001, 2001

2000

FPGA Partitioning with Complex Resource Constraints.

[BibT_eX]

[DOI]

VLSI Design, 2000

Timing-driven routing for symmetrical array-based FPGAs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2000

Simultaneous routing and buffer insertion with restrictions onbuffer locations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Slicing floorplans with range constraint.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Editorial.

[BibT_eX]

[DOI]

Dwight D. Hill

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

A fast hypergraph min-cut algorithm for circuit partitioning.

[BibT_eX]

[DOI]

Integr., 2000

Planning buffer locations by network flows.

[BibT_eX]

[DOI]

Proceedings of the 2000 International Symposium on Physical Design, 2000

Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion.

[BibT_eX]

[DOI]

Proceedings of the 2000 International Symposium on Physical Design, 2000

Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

Meeting Delay Constraints in DSM by Minimal Repeater Insertion.

[BibT_eX]

[DOI]

Adnan Aziz

Proceedings of the 2000 Design, 2000

Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

Optimal low power X OR gate decomposition.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability.

[BibT_eX]

[DOI]

Robert Boone

Proceedings of the 37th Conference on Design Automation, 2000

Wire Routing and Satisfiability Planning.

[BibT_eX]

[DOI]

Esra Erdem

Vladimir Lifschitz

Proceedings of the Computational Logic, 2000

1999

Global routing with crosstalk constraints.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Slicing floorplans with boundary constraints.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Wire-sizing optimization with inductance consideration using transmission-line model.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Optimal shape function for a bidirectional wire under Elmore delay model.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

An efficient and optimal algorithm for simultaneous buffer and wire sizing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Greedy wire-sizing is linear time.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Generation of Universal Series-Parallel Boolean Functions.

[BibT_eX]

[DOI]

J. ACM, 1999

Shaping a VLSI wire to minimize Elmore delay with consideration of coupling capacitance.

[BibT_eX]

[DOI]

Integr., 1999

Slicing floorplans with range constraint.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Physical Design, 1999

A fast hypergraph minimum cut algorithm.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference On Computer Design, 1999

An Exact Tree-Based Structural Technology Mapping Algorithm for Configurable Logic Blocks in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference On Computer Design, 1999

Advances in transistor timing, simulation, and optimization (tutorial abstract).

[BibT_eX]

[DOI]

Jacob White

Jacob Avidan

Ibrahim Abe M. Elfadel

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

A graph theoretic optimal algorithm for schedule compression in time-multiplexed FPGA partitioning.

[BibT_eX]

[DOI]

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Integrated floorplanning and interconnect planning.

[BibT_eX]

[DOI]

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Circuit Partitioning for Dynamically Reconfigurable FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

Error Bounded Padé Approximation via Bilinear Conformal Transformation.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

Slicing Floorplans with Boundary Constraint.

[BibT_eX]

[DOI]

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

Optimal Wire Shape with Consideration of Coupling Capacitance under Elmore Delay Model.

[BibT_eX]

[DOI]

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998

Minimum Crosstalk Vertical Layer Assignment for Three-Layer VHV Channel Routing.

[BibT_eX]

[DOI]

VLSI Design, 1998

Optimal river routing with crosstalk constraints.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 1998

Switch bound allocation for maximizing routability in timing-driven routing of FPGA's.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Optimal min-area min-cut replication in partitioned circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Network-flow-based multiway partitioning with area and pin constraints.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

A matrix synthesis approach to thermal placement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Performance-driven board-level routing for FPGA-based logic emulation.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Integrated partitioning and scheduling for hardware/software co-design.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Slicing floorplans with pre-placed modules.

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Network flow based circuit partitioning for time-multiplexed FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Shaping a VLSI wire to minimize delay using transmission line model.

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Graph matching-based algorithms for FPGA segmentation design.

[BibT_eX]

[DOI]

Jai-Ming Lin

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Performance-Driven Board-Level Routing for FPGA-Based Logic Emulation (Abstract).

[BibT_eX]

[DOI]

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

Circuit Partitioning with Complex Resource Constraints in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs.

[BibT_eX]

[DOI]

Madhukar R. Korupolu

Proceedings of the 35th Conference on Design Automation, 1998

1997

Board-level multiterminal net routing for FPGA-based logic emulation.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 1997

Clock skew minimization during FPGA placement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Circuit clustering for delay minimization under area and pin constraints.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Algorithms for an FPGA switch module routing problem with application to global routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Minimum replication min-cut partitioning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

On optimal board-level routing for FPGA-based logic emulation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Module implementation selection and its application to transistor placement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

How good are slicing floorplans?

[BibT_eX]

[DOI]

F. Y. Young

Integr., 1997

A graph theoretic approach to feed-through pin assignment.

[BibT_eX]

[DOI]

Integr., 1997

On retiming for FPGA logic module minimization.

[BibT_eX]

[DOI]

Integr., 1997

Network flow based multi-way partitioning with area and pin constraints.

[BibT_eX]

[DOI]

Proceedings of the 1997 International Symposium on Physical Design, 1997

Closed form solution to simultaneous buffer insertion/sizing and wire sizing.

[BibT_eX]

[DOI]

Proceedings of the 1997 International Symposium on Physical Design, 1997

Crosstalk-Constrained Maze Routing Based on Lagrangian Relaxation.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

On the Construction of Universal Series-Parallel Functions for Logic Module Design.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Clustering and Load Balancing for Buffered Clock Tree Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Channel Segmentation Design for Symmentrical FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

An exact gate decomposition algorithm for low-power technology mapping.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Optimal shape function for a bi-directional wire under Elmore delay model.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

A new approach to simultaneous buffer insertion and wire sizing.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

A Fast And Accurate Technique To Optimize Characterization Tables For Logic Synthesis.

[BibT_eX]

[DOI]

John F. Croix

Proceedings of the 34st Conference on Design Automation, 1997

Optimal Wire-Sizing Function with Fringing Capacitance Consideration.

[BibT_eX]

[DOI]

Proceedings of the 34st Conference on Design Automation, 1997

1996

Series-parallel functions and FPGA logic module design.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 1996

Universal switch modules for FPGA design.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 1996

Balanced partitioning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Hinted quad trees for VLSI geometry DRC based on efficient searching for neighbors.

[BibT_eX]

[DOI]

Glenn G. Lai

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Echelon: a multilayer detailed area router.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Simultaneous area and delay minimum K-LUT mapping for K-exact networks.

[BibT_eX]

[DOI]

Integr., 1996

Multiplexor Network Generation in High Level Synthesis.

[BibT_eX]

[DOI]

Yung-Ming Fang

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

An optimal algorithm for river routing with crosstalk constraints.

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Optimal non-uniform wire-sizing under the Elmore delay model.

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Universal Logic Modules for Series-Parallel Functions.

[BibT_eX]

[DOI]

Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, 1996

Universal Switch-Module Design for Symmetric-Array-Based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, 1996

An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion.

[BibT_eX]

[DOI]

Y. P. Chen

Proceedings of the 1996 European Design and Test Conference, 1996

Delay Minimal Decomposition of Multiplexers in Technology Mapping.

[BibT_eX]

[DOI]

Shankar Krishnamoorthy

Proceedings of the 33st Conference on Design Automation, 1996

Optimal Wire-Sizing Formular Under the Elmore Delay Model.

[BibT_eX]

[DOI]

Proceedings of the 33st Conference on Design Automation, 1996

Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation.

[BibT_eX]

[DOI]

Proceedings of the 33st Conference on Design Automation, 1996

1995

Optimal net assignment.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Optimum clustering for delay minimization.

[BibT_eX]

[DOI]

Rajmohan Rajaraman

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Performance-driven channel pin assignment algorithms.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

On over-the-cell channel routing with cell orientations consideration.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

An Optimal Layer Assignment Algorithm for Minimizing Crosstalk for Three Layer VHV Channel Routing.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Floorplanning for Low Power Designs.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Thermal placement for high-performance multichip modules.

[BibT_eX]

[DOI]

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Design and analysis of FPGA/FPIC switch modules.

[BibT_eX]

[DOI]

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

FPGA global routing based on a new congestion metric.

[BibT_eX]

[DOI]

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

New algorithms for min-cut replication in partitioned circuits.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Board-level multi-terminal net routing for FPGA-based logic emulation.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Signal integrity optimization on the pad assignment for high-speed VLSI design.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

On Designing ULM-based FPGA Logic Modules.

[BibT_eX]

[DOI]

Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

1994

Channel Density Minimization by Pin Permutation.

[BibT_eX]

[DOI]

VLSI Design, 1994

On shifting blocks and terminals to minimize channel density.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Over-the-Cell Routing with Cell Orientations Consideration.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Efficient network flow based min-cut balanced partitioning.

[BibT_eX]

[DOI]

Honghua Yang

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Simultaneous functional-unit binding and floorplanning.

[BibT_eX]

[DOI]

Yung-Ming Fang

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Layer assignment for high-performance multi-chip modules.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

A new global routing algorithm for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Algorithms for a switch module routing problem.

[BibT_eX]

[DOI]

S. Muthukrishnan

Proceedings of the Proceedings EURO-DAC'94, 1994

Switch Bound Allocation for Maximizing Routability in Timing-Driven Routing of FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 31st Conference on Design Automation, 1994

1993

Efficient via shifting algorithms in channel compaction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

On minimizing the number of L-shaped channels in building-block layout [VLSI].

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Graph-based techniques to speed up floorplan area optimization.

[BibT_eX]

[DOI]

Integr., 1993

A Graph Partitioning Problem for Multiple-chip Design.

[BibT_eX]

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

On optimal approximation of orthogonal polygons.

[BibT_eX]

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Switch module design with application to two-dimensional segmentation design.

[BibT_eX]

[DOI]

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Fast Boolean matching for field-programmable gate arrays.

[BibT_eX]

[DOI]

Proceedings of the European Design Automation Conference 1993, 1993

On over-the-cell channel routing.

[BibT_eX]

[DOI]

Proceedings of the European Design Automation Conference 1993, 1993

Cell area minimization by transistor folding.

[BibT_eX]

[DOI]

Proceedings of the European Design Automation Conference 1993, 1993

Optimal Clustering for Delay Minimization.

[BibT_eX]

[DOI]

Rajmohan Rajaraman

Proceedings of the 30th Design Automation Conference. Dallas, 1993

HV/VH Trees: A New Spatial Data Structure for Fast Region Queries.

[BibT_eX]

[DOI]

Glenn G. Lai

Proceedings of the 30th Design Automation Conference. Dallas, 1993

A note on the Complexity of Stockmeyer's floorplan Optimization Technique.

[BibT_eX]

[DOI]

Proceedings of the Algorithmic Aspects of VLSI Layout, 1993

1992

Optimal floorplan area optimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Topological channel routing [VLSI].

[BibT_eX]

[DOI]

Shinichiro Haruyama

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Channel Density Minimization by Pin Permutation.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

On channel segmentation design for row-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

A Graph Theoretic Technique to Speed up Floorplan Area Optimization.

[BibT_eX]

[DOI]

Proceedings of the 29th Design Automation Conference, 1992

1991

Channel ordering for VLSI layout with rectilinear modules.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

A layout modification approach to via minimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Channel/switchbox definition for VLSI building-block layout.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Optimal channel pin assignment.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Probabilistic Analysis of a Grouping Algorithm.

[BibT_eX]

[DOI]

Edward M. Reingold

Algorithmica, 1991

Area Optimization for Higher Order Hierarchical Floorplans.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

On the Manisfestation of Faults to Errors in Signature Analysis.

[BibT_eX]

[DOI]

John C. Chan

Baxter F. Womack

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Optimal Module Implementation and Its Application to Transistor Placement.

[BibT_eX]

[DOI]

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Minimizing Channel Density by Shifting Blocks and Terminals.

[BibT_eX]

[DOI]

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Efficient shape curve construction in floorplan design.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1991

A General Multi-Layer Area Router.

[BibT_eX]

[DOI]

Proceedings of the 28th Design Automation Conference, 1991

On Minimizing the Number of L-Shaped Channels.

[BibT_eX]

[DOI]

Proceedings of the 28th Design Automation Conference, 1991

1990

Generating more compactable channel routing solutions.

[BibT_eX]

[DOI]

Jingsheng Cong

Integr., 1990

Optimal Orientations of Transistor Chains.

[BibT_eX]

[DOI]

T. H. Freeman

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Topological Routing Using Geometric Information.

[BibT_eX]

[DOI]

Shinichiro Haruyama

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

An Optimal Channel Pin Assignment Algorithm.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Optimal via-shifting in channel compaction.

[BibT_eX]

[DOI]

Proceedings of the European Design Automation Conference, 1990

An Optimal Algorithm for Floorplan Area Optimization.

[BibT_eX]

[DOI]

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

A Channel/Switchbox Definition Algorithm for Building-Block Layout.

[BibT_eX]

[DOI]

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989

An enhanced bottom-up algorithm for floorplan design.

[BibT_eX]

[DOI]

Thomas R. Mueller

Integr., 1989

Floorplan Design of VLSI Circuits.

[BibT_eX]

[DOI]

Algorithmica, 1989

An algorithm for hierarchical floorplan design.

[BibT_eX]

[DOI]

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Efficient Floorplan Area Optimization.

[BibT_eX]

[DOI]

P. S. Sakhamuri

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

VIA Minimization by Layout Modification.

[BibT_eX]

[DOI]

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988

A new approach to three- or four-layer channel routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

Topological channel routing.

[BibT_eX]

[DOI]

Shinichiro Haruyama

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Channel routing order for building-block layout with rectilinear modules.

[BibT_eX]

[DOI]

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

How to Obtain More Compactable Channel Routing Solutions.

[BibT_eX]

[DOI]

Jingsheng Cong

Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987

Algorithmic Aspects of Vlsi Circuit Layout (Channel Routing, Logic Array)

[BibT_eX]

[DOI]

PhD thesis, 1987

Array Optimization for VLSI Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1986

Compacted channel routing with via placement restrictions.

[BibT_eX]

[DOI]

Integr., 1986

A new algorithm for floorplan design.

[BibT_eX]

[DOI]