Xin Zheng

Orcid: 0000-0003-4931-9664

Affiliations:
  • Guangdong University of Technology, School of Automation, School of Microelectronics, Guangzhou, China


According to our database1, Xin Zheng authored at least 24 papers between 2019 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2025
Efficient Design Space Exploration for the BOOM Using SAC-Based Reinforcement Learning.
IEEE Trans. Very Large Scale Integr. Syst., August, 2025

A High-Performance Hardware Accelerator for ECC in GF(p) Over Generic Weierstrass Curves.
IEEE Embed. Syst. Lett., August, 2025

FLALM: A Flexible Low Area-Latency Montgomery Modular Multiplication on FPGA.
IEEE Trans. Computers, January, 2025

A Partial Tag-Data Decoupled Architecture for Last-Level Cache Optimization.
IEEE Comput. Archit. Lett., 2025

2024
An Efficient VCD Parser for Dynamic Power Estimation of Digital Integrated Circuits.
IEEE Embed. Syst. Lett., December, 2024

FPUx: High-Performance Floating-Point Support for Cost-Constrained RISC-V Cores.
IEEE Trans. Very Large Scale Integr. Syst., October, 2024

BSSE: Design Space Exploration on the BOOM With Semi-Supervised Learning.
IEEE Trans. Very Large Scale Integr. Syst., May, 2024

2023
High-performance Reconfigurable DNN Accelerator on a Bandwidth-limited Embedded System.
ACM Trans. Embed. Comput. Syst., November, 2023

Hardware/Software Co-Design of Cryptographic SoC Based on RISC-V Virtual Prototype.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023

2022
A Latent Variable Augmentation Method for Image Categorization with Insufficient Training Samples.
ACM Trans. Knowl. Discov. Data, 2022

An Efficient Image Categorization Method With Insufficient Training Samples.
IEEE Trans. Cybern., 2022

A Dual-Core High-Performance Processor for Elliptic Curve Cryptography in GF(p) Over Generic Weierstrass Curves.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

TiNNA: A Tiny Accelerator for Neural Networks With Efficient DSP Optimization.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A high-performance processor for optimal ate pairing computation over Barreto-Naehrig curves.
IET Circuits Devices Syst., 2022

A high speed processor for elliptic curve cryptography over NIST prime field.
IET Circuits Devices Syst., 2022

High-Performance Cryptographic SoC Virtual Prototyping Platform Based on RISC-V VP.
Proceedings of the HP3C 2022: 6th International Conference on High Performance Compilation, 2022

Design of High-performance SoC Simulation Model Based on Verilator.
Proceedings of the 5th International Conference on Algorithms, 2022

2021
Subgraph feature extraction based on multi-view dictionary learning for graph classification.
Knowl. Based Syst., 2021

Low-Power Reconfigurable Architecture of Elliptic Curve Cryptography for IoT.
IEICE Trans. Electron., 2021

A hardware/software partitioning method based on graph convolution network.
Des. Autom. Embed. Syst., 2021

2020
The Software/Hardware Co-Design and Implementation of SM2/3/4 Encryption/Decryption and Digital Signature System.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A multi-task transfer learning method with dictionary learning.
Knowl. Based Syst., 2020

An efficient multi-label learning method with label projection.
Knowl. Based Syst., 2020

2019
A Resources-Efficient Configurable Accelerator for Deep Convolutional Neural Networks.
IEEE Access, 2019


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