Xueming Li
Orcid: 0000-0002-9700-4272Affiliations:
- Guangdong University of Technology, School of Integrated Circuits, School of Automation, Guangzhou, China
According to our database1,
Xueming Li
authored at least 11 papers
between 2022 and 2025.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2025
A Precision-Scalable Accelerator with Sign-Magnitude Representation and Dual Adder Trees.
ACM Trans. Embed. Comput. Syst., November, 2025
An FPGA Accelerator With Efficient Weight Compression by Combining Bit-Level Sparsity and Mixed-Precision Quantization.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2025
An FPGA-based bit-level weight sparsity and mixed-bit accelerator for neural networks.
J. Syst. Archit., 2025
A precision-scalable sparse CNN accelerator with fine-grained mixed bitwidth configurability.
IEICE Electron. Express, 2025
A DSP-Based Precision-Scalable MAC With Hybrid Dataflow for Arbitrary-Basis-Quantization CNN Accelerator.
IEEE Comput. Archit. Lett., 2025
2023
High-performance Reconfigurable DNN Accelerator on a Bandwidth-limited Embedded System.
ACM Trans. Embed. Comput. Syst., November, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A hardware-efficient computing engine for FPGA-based deep convolutional neural network accelerator.
Microelectron. J., 2022
An efficient loop tiling framework for convolutional neural network inference accelerators.
IET Circuits Devices Syst., 2022
IET Circuits Devices Syst., 2022
An Efficient Parallel Architecture for Convolutional Neural Networks Accelerator on FPGAs.
Proceedings of the HP3C 2022: 6th International Conference on High Performance Compilation, 2022