Xujiang Xiang

According to our database, Xujiang Xiang authored at least 4 papers between 2024 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

Dyn-Bitpool: A 28 nm 27 TOPS/W Two-Sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization.

Xujiang Xiang, Zhiheng Yue, Xiaolong Zhang, Shaojun Wei, Yang Hu, Shouyi Yin

IEEE Trans. Circuits Syst. I Regul. Pap., May, 2025

14.4 A 51.6TFLOPs/W Full-Datapath CIM Macro Approaching Sparsity Bound and <^-30 Loss for Compound AI.

Zhiheng Yue, Xujiang Xiang, Yang Wang, Ruiqi Guo, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2024

15.1 A 0.795fJ/bit Physically-Unclonable Function-Protected TCAM for a Software-Defined Networking Switch.

Zhiheng Yue, Xujiang Xiang, Fengbin Tu, Yang Wang, Yiming Wang, Shaojun Wei, Yang Hu, Shouyi Yin

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

Dyn-Bitpool: A Two-sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization.

Xujiang Xiang, Zhiheng Yue, Yuxuan Li, Liuxin Lv, Shaojun Wei, Yang Hu, Shouyi Yin

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024