Fengbin Tu

According to our database, Fengbin Tu authored at least 51 papers between 2015 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

HDSuper: High-Quality and High Computational Utilization Edge Super-Resolution Accelerator With Hardware-Algorithm Co-Design Techniques.

Xin Zhao, Liang Chang, Dongqi Fan, Zhicheng Hu, Ting Yue, Fengbin Tu, Jun Zhou

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024

MulTCIM: Digital Computing-in-Memory-Based Multimodal Transformer Accelerator With Attention-Token-Bit Hybrid Sparsity.

Fengbin Tu, Zihan Wu, Yiqi Wang, Weiwei Wu, Leibo Liu, Yang Hu, Shaojun Wei, Shouyi Yin

IEEE J. Solid State Circuits, January, 2024

15.1 A 0.795fJ/bit Physically-Unclonable Function-Protected TCAM for a Software-Defined Networking Switch.

Zhiheng Yue, Xujiang Xiang, Fengbin Tu, Yang Wang, Yiming Wang, Shaojun Wei, Yang Hu, Shouyi Yin

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

20.2 A 28nm 74.34TFLOPS/W BF16 Heterogenous CIM-Based Accelerator Exploiting Denoising-Similarity for Diffusion Models.

Ruiqi Guo, Lei Wang, Xiaofeng Chen, Hao Sun, Zhiheng Yue, Yubin Qin, Huiming Han, Yang Wang, Fengbin Tu, Shaojun Wei, Yang Hu, Shouyi Yin

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023

Reconfigurability, Why It Matters in AI Tasks Processing: A Survey of Reconfigurable AI Chips.

Shaojun Wei, Xinhan Lin, Fengbin Tu, Yang Wang, Leibo Liu, Shouyi Yin

IEEE Trans. Circuits Syst. I Regul. Pap., March, 2023

SPCIM: Sparsity-Balanced Practical CIM Accelerator With Optimized Spatial-Temporal Multi-Macro Utilization.

Yiqi Wang, Fengbin Tu, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin

IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023

STAR: An STGCN ARchitecture for Skeleton-Based Human Action Recognition.

Weiwei Wu, Fengbin Tu, Mengqi Niu, Zhiheng Yue, Leibo Liu, Shaojun Wei, Xiangyu Li, Yang Hu, Shouyi Yin

IEEE Trans. Circuits Syst. I Regul. Pap., 2023

SDP: Co-Designing Algorithm, Dataflow, and Architecture for In-SRAM Sparse NN Acceleration.

Fengbin Tu, Yiqi Wang, Ling Liang, Yufei Ding, Leibo Liu, Shaojun Wei, Shouyi Yin, Yuan Xie

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

SPG: Structure-Private Graph Database via SqueezePIR.

Ling Liang, Jilan Lin, Zheng Qu, Ishtiyaque Ahmad, Fengbin Tu, Trinabh Gupta, Yufei Ding, Yuan Xie

Proc. VLDB Endow., 2023

ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration.

Fengbin Tu, Yiqi Wang, Zihan Wu, Ling Liang, Yufei Ding, Bongjin Kim, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin

IEEE J. Solid State Circuits, 2023

TranCIM: Full-Digital Bitline-Transpose CIM-based Sparse Transformer Accelerator With Pipeline/Parallel Reconfigurable Modes.

Fengbin Tu, Zihan Wu, Yiqi Wang, Ling Liang, Liu Liu, Yufei Ding, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin

IEEE J. Solid State Circuits, 2023

A 137.5 TOPS/W SRAM Compute-in-Memory Macro with 9-b Memory Cell-Embedded ADCs and Signal Margin Enhancement Techniques for AI Edge Applications.

Xiaomeng Wang, Fengshi Tian, Xizi Chen, Jiakun Zheng, Xuejiao Liu, Fengbin Tu, Jie Yang, Mohamad Sawan, Kwang-Ting Cheng, Chi-Ying Tsui

CoRR, 2023

Towards Efficient Control Flow Handling in Spatial Architecture via Architecting the Control Flow Plane.

Jinyi Deng, Xinru Tang, Jiahao Zhang, Yuxuan Li, Linyun Zhang, Fengbin Tu, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin

CoRR, 2023

DyBit: Dynamic Bit-Precision Numbers for Efficient Quantized Neural Network Inference.

Jiajun Zhou, Jiajun Wu, Yizhao Gao, Yuhao Ding, Chaofan Tao, Boyu Li, Fengbin Tu, Kwang-Ting Cheng, Hayden Kwok-Hay So, Ngai Wong

CoRR, 2023

Towards Efficient Control Flow Handling in Spatial Architecture via Architecting the Control Flow Plane.

Jinyi Deng, Xinru Tang, Jiahao Zhang, Yuxuan Li, Linyun Zhang, Boxiao Han, Hongjun He, Fengbin Tu, Leibo Liu, Shaojun Wei, Yang Hu, Shouyi Yin

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

TensorCIM: A 28nm 3.7nJ/Gather and 8.3TFLOPS/W FP32 Digital-CIM Tensor Processor for MCM-CIM-Based Beyond-NN Acceleration.

Fengbin Tu, Yiqi Wang, Zihan Wu, Weiwei Wu, Leibo Liu, Yang Hu, Shaojun Wei, Shouyi Yin

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

MuITCIM: A 28nm $2.24 \mu\mathrm{J}$/Token Attention-Token-Bit Hybrid Sparse Digital CIM-Based Accelerator for Multimodal Transformers.

Fengbin Tu, Zihan Wu, Yiqi Wang, Weiwei Wu, Leibo Liu, Yang Hu, Shaojun Wei, Shouyi Yin

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

ECSSD: Hardware/Data Layout Co-Designed In-Storage-Computing Architecture for Extreme Classification.

Siqi Li, Fengbin Tu, Liu Liu, Jilan Lin, Zheng Wang, Yangwook Kang, Yufei Ding, Yuan Xie

Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

BIOS: A 40nm Bionic Sensor-defined 0.47pJ/SOP, 268.7TSOPs/W Configurable Spiking Neuron-in-Memory Processor for Wearable Healthcare.

Fengshi Tian, Xiaomeng Wang, Jinbo Chen, Jiakun Zheng, Hui Wu, Xuejiao Liu, Fengbin Tu, Jie Yang, Mohamad Sawan, Chi-Ying Tsui, Kwang-Ting (Tim) Cheng

Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

PIM-HLS: An Automatic Hardware Generation Tool for Heterogeneous Processing-In-Memory-based Neural Network Accelerators.

Yu Zhu, Zhenhua Zhu, Guohao Dai, Fengbin Tu, Hanbo Sun, Kwang-Ting Cheng, Huazhong Yang, Yu Wang

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

AutoDCIM: An Automated Digital CIM Compiler.

Jia Chen, Fengbin Tu, Kunming Shao, Fengshi Tian, Xiao Huo, Chi-Ying Tsui, Kwang-Ting Cheng

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

GQNA: Generic Quantized DNN Accelerator With Weight-Repetition-Aware Activation Aggregating.

Jianxun Yang, Fengbin Tu, Yixuan Li, Yiqi Wang, Leibo Liu, Shaojun Wei, Shouyi Yin

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

H2Learn: High-Efficiency Learning Accelerator for High-Accuracy Spiking Neural Networks.

Ling Liang, Zheng Qu, Zhaodong Chen, Fengbin Tu, Yujie Wu, Lei Deng, Guoqi Li, Peng Li, Yuan Xie

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Dynamic Sparse Attention for Scalable Transformer Acceleration.

Liu Liu, Zheng Qu, Zhaodong Chen, Fengbin Tu, Yufei Ding, Yuan Xie

IEEE Trans. Computers, 2022

A 28nm 15.59µJ/Token Full-Digital Bitline-Transpose CIM-Based Sparse Transformer Accelerator with Pipeline/Parallel Reconfigurable Modes.

Fengbin Tu, Zihan Wu, Yiqi Wang, Ling Liang, Liu Liu, Yufei Ding, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration.

Fengbin Tu, Yiqi Wang, Zihan Wu, Ling Liang, Yufei Ding, Bongjin Kim, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

INSPIRE: in-storage private information retrieval via protocol and architecture co-design.

Jilan Lin, Ling Liang, Zheng Qu, Ishtiyaque Ahmad, Liu Liu, Fengbin Tu, Trinabh Gupta, Yufei Ding, Yuan Xie

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

Accelerating Spatiotemporal Supervised Training of Large-Scale Spiking Neural Networks on GPU.

Ling Liang, Zhaodong Chen, Lei Deng, Fengbin Tu, Guoqi Li, Yuan Xie

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Alleviating datapath conflicts and design centralization in graph analytics acceleration.

Haiyang Lin, Mingyu Yan, Duo Wang, Mo Zou, Fengbin Tu, Xiaochun Ye, Dongrui Fan, Yuan Xie

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

DOTA: detect and omit weak attentions for scalable transformer acceleration.

Zheng Qu, Liu Liu, Fengbin Tu, Zhaodong Chen, Yufei Ding, Yuan Xie

Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022

2021

Erratum to "Evolver: a Deep Learning Processor With On-Device Quantization-Voltage-Frequency Tuning".

Fengbin Tu, Weiwei Wu, Yang Wang, Hongjiang Chen, Feng Xiong, Man Shi, Ning Li, Jinyi Deng, Tianbao Chen, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin

IEEE J. Solid State Circuits, 2021

Evolver: A Deep Learning Processor With On-Device Quantization-Voltage-Frequency Tuning.

Fengbin Tu, Weiwei Wu, Yang Wang, Hongjiang Chen, Feng Xiong, Man Shi, Ning Li, Jinyi Deng, Tianbao Chen, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin

IEEE J. Solid State Circuits, 2021

Brain-Inspired Computing: Adventure from Beyond CMOS Technologies to Beyond von Neumann Architectures ICCAD Special Session Paper.

Hussam Amrouch, Jian-Jia Chen, Kaushik Roy, Yuan Xie, Indranil Chakraborty, Wenqin Huangfu, Ling Liang, Fengbin Tu, Cheng Wang, Mikail Yayla

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

ADROIT: An Adaptive Dynamic Refresh Optimization Framework for DRAM Energy Saving In DNN Training.

Xinhan Lin, Liang Sun, Fengbin Tu, Leibo Liu, Xiangyu Li, Shaojun Wei, Shouyi Yin

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

DUET: Boosting Deep Neural Network Efficiency on Dual-Module Architecture.

Liu Liu, Zheng Qu, Lei Deng, Fengbin Tu, Shuangchen Li, Xing Hu, Zhenyu Gu, Yufei Ding, Yuan Xie

Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

STC: Significance-aware Transform-based Codec Framework for External Memory Access Reduction.

Feng Xiong, Fengbin Tu, Man Shi, Yang Wang, Leibo Liu, Shaojun Wei, Shouyi Yin

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory.

Shouyi Yin, Shibin Tang, Xinhan Lin, Peng Ouyang, Fengbin Tu, Leibo Liu, Jishen Zhao, Cong Xu, Shuangchen Li, Yuan Xie, Shaojun Wei

IEEE Trans. Parallel Distributed Syst., 2019

Reconfigurable Architecture for Neural Approximation in Multimedia Computing.

Fengbin Tu, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei

IEEE Trans. Circuits Syst. Video Technol., 2019

A High Throughput Acceleration for Hybrid Neural Networks With Efficient Resource Management on FPGA.

Shouyi Yin, Shibin Tang, Xinhan Lin, Peng Ouyang, Fengbin Tu, Leibo Liu, Shaojun Wei

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

MoNA: Mobile Neural Architecture with Reconfigurable Parallel Dimensions.

Weiwei Wu, Shouyi Yin, Fengbin Tu, Leibo Liu, Shaojun Wei

Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

Towards Efficient Compact Network Training on Edge-Devices.

Feng Xiong, Fengbin Tu, Shouyi Yin, Shaojun Wei

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

2018

GNA: Reconfigurable and Efficient Architecture for Generative Network Acceleration.

Jiale Yan, Shouyi Yin, Fengbin Tu, Leibo Liu, Shaojun Wei

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications.

Shouyi Yin, Peng Ouyang, Shibin Tang, Fengbin Tu, Xiudong Li, Shixuan Zheng, Tianyi Lu, Jiangyuan Gu, Leibo Liu, Shaojun Wei

IEEE J. Solid State Circuits, 2018

An Energy Efficient JPEG Encoder with Neural Network Based Approximation and Near-Threshold Computing.

Zhihui Wang, Shouyi Yin, Fengbin Tu, Leibo Liu, Shaojun Wei

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Bit-width Adaptive Accelerator Design for Convolution Neural Network.

Jianxin Guo, Shouyi Yin, Peng Ouyang, Fengbin Tu, Shibin Tang, Leibo Liu, Shaojun Wei

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

RANA: Towards Efficient Neural Acceleration with Refresh-Optimized Embedded DRAM.

Fengbin Tu, Weiwei Wu, Shouyi Yin, Leibo Liu, Shaojun Wei

Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

LCP: a layer clusters paralleling mapping method for accelerating inception and residual networks on FPGA.

Xinhan Lin, Shouyi Yin, Fengbin Tu, Leibo Liu, Xiangyu Li, Shaojun Wei

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns.

Fengbin Tu, Shouyi Yin, Peng Ouyang, Shibin Tang, Leibo Liu, Shaojun Wei

IEEE Trans. Very Large Scale Integr. Syst., 2017

AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs.

Shibin Tang, Shouyi Yin, Shixuan Zheng, Peng Ouyang, Fengbin Tu, Leiyue Yao, JinZhou Wu, Wenming Cheng, Leibo Liu, Shaojun Wei

Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017

2015

Neural approximating architecture targeting multiple application domains.

Fengbin Tu, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

RNA: a reconfigurable architecture for hardware neural acceleration.

Fengbin Tu, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015