Fengbin Tu

According to our database1, Fengbin Tu authored at least 20 papers between 2015 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2021
Erratum to "Evolver: a Deep Learning Processor With On-Device Quantization-Voltage-Frequency Tuning".
IEEE J. Solid State Circuits, 2021

Evolver: A Deep Learning Processor With On-Device Quantization-Voltage-Frequency Tuning.
IEEE J. Solid State Circuits, 2021

H2Learn: High-Efficiency Learning Accelerator for High-Accuracy Spiking Neural Networks.
CoRR, 2021

2020
DUET: Boosting Deep Neural Network Efficiency on Dual-Module Architecture.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

STC: Significance-aware Transform-based Codec Framework for External Memory Access Reduction.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory.
IEEE Trans. Parallel Distributed Syst., 2019

Reconfigurable Architecture for Neural Approximation in Multimedia Computing.
IEEE Trans. Circuits Syst. Video Technol., 2019

A High Throughput Acceleration for Hybrid Neural Networks With Efficient Resource Management on FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

MoNA: Mobile Neural Architecture with Reconfigurable Parallel Dimensions.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

Towards Efficient Compact Network Training on Edge-Devices.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

2018
GNA: Reconfigurable and Efficient Architecture for Generative Network Acceleration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications.
IEEE J. Solid State Circuits, 2018

An Energy Efficient JPEG Encoder with Neural Network Based Approximation and Near-Threshold Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Bit-width Adaptive Accelerator Design for Convolution Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

RANA: Towards Efficient Neural Acceleration with Refresh-Optimized Embedded DRAM.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

LCP: a layer clusters paralleling mapping method for accelerating inception and residual networks on FPGA.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns.
IEEE Trans. Very Large Scale Integr. Syst., 2017

AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs.
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017

2015
Neural approximating architecture targeting multiple application domains.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

RNA: a reconfigurable architecture for hardware neural acceleration.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015


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