Yang Zhang
Orcid: 0000-0003-0712-1537Affiliations:
- Chinese University of Hong Kong, Department of Electronic Engineering, Hong Kong
According to our database1,
Yang Zhang
authored at least 11 papers
between 2017 and 2021.
Collaborative distances:
Collaborative distances:
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on orcid.org
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Bibliography
2021
A 0.59-mW 78.7-dB SNDR 2-MHz Bandwidth Active-RC Delta-Sigma Modulator With Relaxed and Reduced Amplifiers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
2020
A 0.032-mm<sup>2</sup> 43.3-fJ/Step 100-200-MHz IF 2-MHz Bandwidth Bandpass DSM Based on Passive N-Path Filters.
IEEE J. Solid State Circuits, 2020
A Power-Efficient 10-MHz Bandwidth Active-RC CTDSM with a Charge-Recycled Highly-Linear 5-Level SC DAC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A Highly Linear Multi-Level SC DAC in a Power-Efficient Gm-C Continuous-Time Delta-Sigma Modulator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A 0.4-V 0.2 pJ/step 90-dB SNDR 20-kHz CT delta-sigma modulator using class-AB amplifier with a novel local common-mode feedback.
IEICE Electron. Express, 2019
An Automatic On-Chip Calibration Technique for Static and Dynamic DAC Error Correction in High-Speed Continuous-Time Delta-Sigma Modulators.
IEEE Access, 2019
2018
Improving Power Efficiency for Active-RC Delta-Sigma Modulators Using a Passive-RC Low-Pass Filter in the Feedback.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Power-Efficient Active-RC CT DSM with a Lowpass Capacitor at the Virtual Ground Node of the First Integrator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Proceedings of the International SoC Design Conference, 2017