Kong-Pang Pun

Orcid: 0000-0001-7736-0811

Affiliations:
  • Chinese University of Hong Kong


According to our database1, Kong-Pang Pun authored at least 115 papers between 1998 and 2024.

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Bibliography

2024
Lightweight, error-tolerant edge detection using memristor-enabled stochastic logics.
CoRR, 2024

2023
A Low-Power Keyword Spotting System With High-Order Passive Switched-Capacitor Bandpass Filters for Analog-MFCC Feature Extraction.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2023

A 13-Level SC DAC Achieving High Linearity With a Simple DEM for Wideband CT DSMs.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

A 10-MHz 85.1-dB SFDR 1.1-mW continuous-time Delta-sigma modulator employing calibration-free SC DAC and passive front-end low-pass filter.
Microelectron. J., 2023

2021
A 0.59-mW 78.7-dB SNDR 2-MHz Bandwidth Active-RC Delta-Sigma Modulator With Relaxed and Reduced Amplifiers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A 270 nW Switched-Capacitor Acoustic Feature Extractor for Always-On Voice Activity Detection.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A Current-Switching Technique for Intra-Body Communication With Miniaturized Electrodes.
IEEE Trans. Biomed. Circuits Syst., 2021

2020
A 9.6 nW, 8-Bit, 100 S/s Envelope-to-Digital Converter for Respiratory Monitoring.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A 0.032-mm<sup>2</sup> 43.3-fJ/Step 100-200-MHz IF 2-MHz Bandwidth Bandpass DSM Based on Passive N-Path Filters.
IEEE J. Solid State Circuits, 2020

A Power-Efficient 10-MHz Bandwidth Active-RC CTDSM with a Charge-Recycled Highly-Linear 5-Level SC DAC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Power-Efficient Gm-C DSMs With High Immunity to Aliasing, Clock Jitter, and ISI.
IEEE Trans. Very Large Scale Integr. Syst., 2019

An Extremely Linear Multi-Level DAC for Continuous-Time Delta-Sigma Modulators.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A Highly Linear Multi-Level SC DAC in a Power-Efficient Gm-C Continuous-Time Delta-Sigma Modulator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 0.4-V 0.2 pJ/step 90-dB SNDR 20-kHz CT delta-sigma modulator using class-AB amplifier with a novel local common-mode feedback.
IEICE Electron. Express, 2019

An Automatic On-Chip Calibration Technique for Static and Dynamic DAC Error Correction in High-Speed Continuous-Time Delta-Sigma Modulators.
IEEE Access, 2019

2018
An SAR ADC Switching Scheme With MSB Prediction for a Wide Input Range and Reduced Reference Voltage.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Improving Power Efficiency for Active-RC Delta-Sigma Modulators Using a Passive-RC Low-Pass Filter in the Feedback.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A Gm-C Delta-Sigma Modulator With a Merged Input-Feedback Gm Circuit for Nonlinearity Cancellation and Power Efficiency Enhancement.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Self-Clocked Resistive CMOS Smart Temperature Sensor for Wireless Sensor Networks.
J. Circuits Syst. Comput., 2018

Power-Efficient Active-RC CT DSM with a Lowpass Capacitor at the Virtual Ground Node of the First Integrator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An On-Chip Static and Dynamic DAC Error Correction Technique for High Speed Multibit Delta-Sigma Modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Continuous-time delta-sigma modulator with an upfront passive-RC low-pass network.
Proceedings of the International SoC Design Conference, 2017

2016
A 10-bit 2 MS/s SAR ADC using reverse VCM-based switching scheme.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Gm-cell nonlinearity compensation technique using single-bit quantiser and FIR DAC in Gm-C based delta-sigma modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
A 5.4-mW 180-cm Transmission Distance 2.5-Mb/s Advanced Techniques-Based Novel Intrabody Communication Receiver Analog Front End.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A Resistor-Based Sub-1-V CMOS Smart Temperature Sensor for VLSI Thermal Management.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A Charge Recycling SAR ADC With a LSB-Down Switching Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 5-ps Vernier sub-ranging time-to-digital converter with DNL calibration.
Microelectron. J., 2015

Next-Generation Delta-Sigma Converters: Trends and Perspectives.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Guest Editorial: Next-Generation Delta-Sigma Converters.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

2014
Optimizing the Stage Resolution in Pipelined SAR ADCs for High-Speed High-Resolution Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

A High-Linearity Capacitance-to-Digital Converter Suppressing Charge Errors From Bottom-Plate Switches.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A High Image-Rejection SC Quadrature Bandpass DSM for Low-IF Receivers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Design considerations of calibration DAC in self-calibrated SAR A/D converters.
Microelectron. J., 2014

Simplifying HOG arithmetic for speedy hardware realization.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
Architecture and Design Flow for a Highly Efficient Structured ASIC.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Unit capacitor array based SAR ADC.
Microelectron. Reliab., 2013

A continuous-time cascaded delta-sigma modulator with PMW-based automatic RC time constant tuning and correlated double sampling.
Microelectron. J., 2013

2012
A charge-pump and comparator based power-efficient pipelined ADC technique.
Microelectron. J., 2012

Low-offset comparator using capacitive self-calibration.
Proceedings of the International SoC Design Conference, 2012

Novel overshoot cancellation in comparator-based pipelined ADC.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Analysis and Design of a 14-bit SAR ADC using self-calibration DAC.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
A chopper-stabilized high-pass Delta-Sigma Modulator with reduced chopper charge injection.
Microelectron. J., 2011

A Novel Switched-Current Successive Approximation ADC.
J. Circuits Syst. Comput., 2011

2010
A 0.5-Hz High-Pass Cutoff Dual-Loop Transimpedance Amplifier for Wearable NIR Sensing Device.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

A Low-Power Continuously-Calibrated Clock Recovery Circuit for UHF RFID EPC Class-1 Generation-2 Transponders.
IEEE J. Solid State Circuits, 2010

RF Module Design of Passive UHF RFID Tag Implemented in CMOS 90-nm Technology.
J. Low Power Electron., 2010

Practical placement and routing techniques for analog circuit designs.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Structured ASIC: Methodology and comparison.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Design of a single layer programmable Structured ASIC library.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Rapid prototyping on a structured ASIC fabric.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
A 0.5-V Wideband Amplifier for a 1-MHz CT Complex Delta-Sigma Modulator.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

Special Issue on Circuits and Systems Solutions for Nanoscale CMOS Design Challenges.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

A Novel Mismatch Cancellation and I/Q Channel Multiplexing Scheme for Quadrature Bandpass DeltaSigma Modulators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A Low-power Signal Processing Front-end and Decoder for UHF Passive RFID Transponders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A comparison of via-programmable gate array logic cell circuits.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

2008
A Fully Differential Band-Selective Low-Noise Amplifier for MB-OFDM UWB Receivers.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

A Low-Power CMOS Front-End for Photoplethysmographic Signal Acquisition With Robust DC Photocurrent Rejection.
IEEE Trans. Biomed. Circuits Syst., 2008

Design of passive UHF RFID tag in 130nm CMOS technology.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Enhanced channel selection using digital low-IF in Weaver receiver architecture.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
A Speech Recognition IC Using Hidden Markov Models with Continuous Observation Densities.
J. VLSI Signal Process., 2007

Power-Efficient VLSI Realization of a Complex FSM for H.264/AVC Bitstream Parsing.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Correction to "A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC".
IEEE J. Solid State Circuits, 2007

Author's Response.
IEEE J. Solid State Circuits, 2007

A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC.
IEEE J. Solid State Circuits, 2007

Priority-Based Heading One Detector in H.264/AVC Decoding.
EURASIP J. Embed. Syst., 2007

A DEM Scheme for I/Q Mismatch Compensation in Multi-Bit CT Delta Sigma Modulator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Analog placement with common centroid constraints.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006
A 75-dB image rejection IF-input quadrature-sampling SC ΣΔ Modulator.
IEEE J. Solid State Circuits, 2006

A 0.5V 74dB SNDR 25kHz CT ΔΣ Modulator with Return-to-Open DAC.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Power-efficient VLSI implementation of bitstream parsing in H.264/AVC decoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An ECG measurement IC using driven-right-leg circuit.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A fully differential low noise amplifier with real-time channel hopping for ultra-wideband wireless applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An optimal normal basis elliptic curve cryptoprocessor for inductive RFID application.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 0.5V fully differential OTA with local common feedback.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An efficient MFCC extraction method in speech recognition.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 6-digit CMOS current-mode analog-to-quaternary converter with RSD error correction algorithm.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Adiabatic Smart Card.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

0.8 V GPS band CMOS VCO with 29% Tuning Range.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Sub-1 V Current Mode CMOS Integrated Receiver Front-end for GPS System.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
A near-infrared heart rate measurement IC with very low cutoff frequency using current steering technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Active RC filter with reduced capacitance by current division technique.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A near-infrared heart rate sensor IC with very low cutoff frequency using current steering technique.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Ramp voltage supply using adiabatic charging principle.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Realization of card-centric framework: a card-centric computer [smart cards].
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A speech recognizer with selectable model parameters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A 75dB image rejection IF-input quadrature sampling SC ΣΔ modulator.
Proceedings of the 31st European Solid-State Circuits Conference, 2005

2004
Preparing smartcard for the future: from passive to active.
IEEE Trans. Consumer Electron., 2004

An I/Q mismatch-free switched-capacitor complex sigma-delta Modulator.
IEEE Trans. Circuits Syst. II Express Briefs, 2004

A low-latency asynchronous shift register.
IEEE Trans. Circuits Syst. II Express Briefs, 2004

A high-efficiency strongly self-checking asynchronous datapath.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Pipelines in Dynamic Dual-Rail Circuits.
Proceedings of the Integrated Circuit and System Design, 2004

An IF-sampling SC complex lowpass Sigma Delta modulator with high image rejection by capacitor sharing.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An asynchronous SOVA decoder for wireless communication application.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An IF input continuous-time sigma-delta analog-digital converter with high image rejection.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter.
Proceedings of the Field Programmable Logic and Application, 2004

Card-Centric Framework - Providing I/O Resources for Smart Cards.
Proceedings of the Smart Card Research and Advanced Applications VI, 2004

A low power asynchronous Java processor for contactless smart card.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Quadrature sampling schemes with improved image rejection.
IEEE Trans. Circuits Syst. II Express Briefs, 2003

Reversed nested Miller compensation with voltage buffer and nulling resistor.
IEEE J. Solid State Circuits, 2003

Design for Self-Checking and Self-Timed Datapath.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Clock recovery circuit with adiabatic technology (quasi-static CMOS logic).
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A low power asynchronous GF(2<sup>173</sup>) ALU for elliptic curve crypto-processor.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

An HMM-based speech recognition IC.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

An FPGA-based re-configurable 24-bit 96kHz sigma-delta audio DAC.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

A contactless smartcard designed with asynchronous circuit technique.
Proceedings of the ESSCIRC 2003, 2003

2002
A quadrature IF mixer with high image rejection for continuous-time complex Sigma-Delta modulators.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A CMOS current feedback operational amplifier with active current mode compensation.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A 1.2 V 900 MHz CMOS mixer.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A Totally Self-Checking Dynamic Asynchronous Datapath.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

A 900 MHz 1.2 V CMOS mixer with high linearity.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001
A quadrature sampling scheme with improved image rejection for complex-IF receivers.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
Wideband digital correction of I and Q mismatch in quadrature radio receivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
Poly-phase switched-capacitor IIR Hilbert transformers.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998
Basic principles and new solutions for analog sampled-data image rejection mixers.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998


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